Magma announces agenda for MUSIC Silicon Valley users conference

SAN JOSE, USA: Magma Design Automation Inc. has announced the final agenda for the MUSIC users conference in Silicon Valley on March 10 in San Jose.

The program will feature parallel tracks of technical presentations and tutorials given by Magma users, design industry experts and Magma's engineering research and development staff, and an exposition of Magma partners. Magma CEO Rajeev Madhavan will deliver a keynote address entitled, "The Electronic Ocean."

MUSIC provides an open forum for users to gain expertise using Magma's chip design software, and to exchange ideas about and solutions for the challenges of analog and integrated circuit and system-on-chip (SoC) designs.

Over the years, MUSIC has become a leading venue for Magma users to gather, share and learn best practices and solutions. This year's program covers a range of Magma software capabilities including synthesis, placement and routing, floorplanning, library characterization, verification, circuit simulation and analog design. Users will share useful tips on how to leverage Magma software to improve results, reduce power, minimize costs and increase productivity.

User presentations will include:
* 65nm design tapeout in six weeks.
* Case study: Low power design.
* Comparing crosstalk delay calculations in Talus and Prime Time-SI.
* Accelerating timing closure on large, complex nanometer designs.
* Multimode/multi-corner analysis using Talus Flow Manager.
* Timing closure challenges and solutions.
* Magma Talus design with scan test compression.
* SynTest DFT in the Magma design flow.
* At-speed functional verification of complex IOs using FineSim SPICE.
* A high-capacity power integrity flow supporting inductive rail effects with transistor-level accuracy.
* Using the Titan shape-based-router for next-generation Flash-based FPGAs.
* The role of design and test methodologies in IC diagnosis.

Magma will present the following tutorials:

* Solving design challenges visually with the Talus Visual Volcano.
* Using SiliconSmart ACE and embedded FineSim simulator for 28nm standard I/O cell and memory characterization.

The MUSIC agenda will also feature a guest keynote and a luncheon panel. Robert Patti, CTO and vice president of Design Engineering at Tezzaron Semiconductor, will present, "3D Integrated Circuits: New Directions for Semiconductors."

Venture capitalists from Farallon Advisors, LLC, Foundation Capital, Intel Capital and US Venture Partners will participate in a panel entitled, "Semiconductor Venture Funding – At a Crossroads?" moderated by Jorge del Calvo of Pillsbury Winthrop Shaw Pittman LLP.