Vitesse's new forward error correction technology accelerates migration to 100G

OFC/NFOEC 2010, SAN DIEGO, USA: Vitesse Semiconductor Corp. announced the immediate availability of its enhanced forward error correction (eFEC) technology for implementation in ASICs or FPGAs.

Vitesse's new, patented Continuously Interleaved BCH (CI-BCH™) eFEC code offers the highest performing hard decision eFEC available today and is the industry’s only eFEC implementable in single FPGA form at 100G. Compared to today's FEC solutions, applying Vitesse's CI-BCH eFEC enables both 40G and 100G backbones to operate over 25-50% longer spans, respectively, with lower power, lower cost, and lower latency.

As service providers upgrade 10G metro and long-haul networks to 100G speed, optical signal-to-noise ratio (OSNR) rapidly degrades due to amplified spontaneous emission noise. Left uncompensated, this OSNR degradation results in unacceptable transmission error rates. Additionally, the complexity of implementation increases exponentially as data rates increase. Enhanced FEC is better able to correct the increased error rates and support error free delivery over longer distances.

“Carriers are deploying 40G and 100G because the economics make sense; these are no longer science projects. The 40G optical market grew rapidly during 2009, with port shipment roughly doubling every year when compared to the previous years,” according to Andrew Schmitt, directing analyst, optical, Infonetics Research. “Based on their strong technology and market position, vendors such as Vitesse should benefit from both 40G and 100G as each market evolves.”

Available for both FPGAs and ASICs, Vitesse's CI-BCH code is offered at 7 percent and 20 percent FEC overhead for 40G and 100G implementations, respectively. The 7 percent overhead version offers 9.35 dB net electrical coding gain (NECG). The 20 percent version provides up to 10.5 dB NECG. The CI version of a class of base codes called BCH represents a unique advance in FEC codes, with superior performance to any block codes offered to date.

Vitesse’s CI-BCH is the industry’s first eFEC to solve the implementation complexity issues associated with higher data rates. Both versions of Vitesse's code deliver superior performance at the lowest latency and power dissipation, as well as the smallest gate count, compared to current FEC alternatives.

High-gain error correcting codes developed over the last two decades share the attribute that solving one base code word helps improve the ability to solve other base code words at intersecting bit locations. Prior to Vitesse's work, high-gain, block-style codes developed for FEC have not been able to fully utilize this “codeword helping codeword” phenomena. Vitesse's CI-BCH takes advantage of “codeword helping codeword” to improve coding gain while reducing the cost of hardware implementation significantly.

For latency sensitive applications, the design offers a variable latency decoder using a common encoder, allowing lower latency to be achieved at the expense of coding gain. The decoder additionally collects FEC-corrected error statistics.