Monday, May 31, 2010

Fraunhofer IZM orders 300mm Pegasus DSi deep silicon etch system on an Omega fxP platform from SPTS for 3D-IC TSV app

NEWPORT, WALES: SPP Process Technology Systems (SPTS), a supplier of advanced semiconductor capital equipment and process technologies for the global semiconductor industry and related markets, has received an order for a Pegasus DSi Deep Silicon etch system supported on the Omega fxP cluster platform, for 3D-IC through silicon via (TSV) application from Fraunhofer IZM, to be installed at All Silicon System Integration Dresden (ASSID).

ASSID is a brand new center which has been set up by Fraunhofer IZM Berlin to develop 3D wafer level technologies on 300mm wafers, enabling leading device manufacturers to apply 3D-IC technology in high volume production to enhance the performance, functionality and scaling requirements of their future products. The new 300mm Pegasus DSi system will be used to etch deep through silicon vias (TSV), and for wafer thinning applications.

M. Juergen Wolf, the Coordinator and Manager of Fraunhofer IZM-ASSID explained: "Our new center has a state-of-the-art clean-room facility and SPTS, as a key cooperation partner, provides valuable experience and production-qualified equipment for our 300mm 3D device stacking assembly line. The complete line will include TSV formation, TSV post-processing on wafer frontside and backside, as well as testing and failure analysis."

"We recognize the significance of IZM's contributions to definitive TSV technology, and are honoured that Fraunhofer has decided to extend that technological leadership with SPTS," remarked Susumu Kaminaga, Chairman of SPTS and President of Sumitomo Precision Products (SPP).

Kevin T. Crofton, Managing Director of the Single Wafer Division of SPTS, added: "We are delighted that Fraunhofer IZM has selected SPTS for this important program. IZM is a long time supporter of our equipment at 200mm, and it is testament to our support and technology that they have chosen to continue that relationship at 300mm. We look forward to helping IZM develop and implement 3D-IC processes inside the new ASSID facility, and ultimately into volume manufacture."

Intel unveils new product plans for high-performance computing

SANTA CLARA, USA & HAMBURG, GERMANY: During the International Supercomputing Conference (ISC), Intel Corp. announced plans to deliver new products based on the Intel Many Integrated Core (MIC) architecture that will create platforms running at trillions of calculations per second, while also retaining the benefits of standard Intel processors.

Targeting high-performance computing segments such as exploration, scientific research and financial or climate simulation, the first product, codenamed “Knights Corner,” will be made on Intel’s 22-nanometer manufacturing (nm) process – using transistor structures as small as 22 billionths of a meter – and will use Moore’s Law to scale to more than 50 Intel processing cores on a single chip.

While the vast majority of workloads will still run best on award-winning Intel Xeon processors, Intel MIC architecture will help accelerate select highly parallel applications.

Industry design and development kits codenamed “Knights Ferry” are currently shipping to select developers, and beginning in the second half of 2010, Intel will expand the program to deliver an extensive range of developer tools for Intel MIC architecture.

Common Intel software tools and optimization techniques between Intel MIC architecture and Intel Xeon processors will support diverse programming models that will place unprecedented performance in the hands of scientists, researchers and engineers, allowing them to increase their pace of discovery and preserve their existing software investments.

The Intel MIC architecture is derived from several Intel projects, including “Larrabee” and such Intel Labs research projects as the Single-chip Cloud Computer.

“The CERN openlab team was able to migrate a complex C++ parallel benchmark to the Intel MIC software development platform in just a few days,” said Sverre Jarp, CTO of CERN openlab. "The familiar hardware programming model allowed us to get the software running much faster than expected.”

“Intel’s Xeon processors, and now our new Intel® Many Integrated Core architecture products, will further push the boundaries of science and discovery as Intel accelerates solutions to some of humanity’s most challenging problems,” said Kirk Skaugen, vice president and general manager of Intel’s Data Center Group.

“The Intel MIC architecture will extend Intel’s leading HPC products and solutions that are already in nearly 82 percent of the world’s top supercomputers. Today’s investments are indicative of Intel’s growing commitment to the global HPC community.”

The 35th edition of the TOP500 list, which was announced at ISC, shows that Intel continues to be the platform of choice in high-performance computing, with 408 systems, or nearly 82 percent, powered by Intel processors.

More than 90 percent of quad-core-based systems use Intel processors, with the Intel Xeon 5500 series processor nearly doubling its presence with 186 systems. Intel chips also power three systems in the top 10, and four out of five new entrants in the top 30.

Seven systems contain the recently announced Intel Xeon 5600 series processor, codenamed “Westmere-EP,” and two systems are powered by the new Intel Xeon 7500 series processor, codenamed “Nehalem-EX.”

The Intel Xeon processor 5600 series is playing the vital role in the highest-ranked system from China in the history of the Top500. The No. 2 system, located at the National Supercomputing Center (NSCS) in Shenzhen, reached 1.2 petaflops on the Linpack benchmark with a Dawning TC3600. NSCS is a hub for research and innovation in China.

The semi-annual TOP500 list of supercomputers is the work of Hans Meuer of the University of Mannheim, Erich Strohmaier and Horst Simon of the U.S. Department of Energy’s National Energy Research Scientific Computing Center, and Jack Dongarra of the University of Tennessee.

New Exascale lab
To meet the growing challenge of running large-scale simulations in the multi petaflops and exaflops range of computing, Intel, Forschungszentrum Julich (FZJ) and ParTec will announce a multi-year commitment to create the ExaCluster Laboratory (ECL) at Julich.

The lab will develop key technologies, tools and methods to power multi petaflops and exaflops machines, focusing on the scalability and resilience of those systems. ECL will become the latest member of Intel Labs Europe, a network of research and innovation centers spanning Europe.

AMD Opteron processor again dominates TOP500

International Supercomputing Conference 2010, SUNNYVALE, USA: AMD continues to hold the reigning spot on the TOP500 Supercomputer list announced at the International Supercomputing Conference in Hamburg, Germany.

Jaguar, the world’s highest performing system, is a massive, 1.75 petaflop Cray XT5 supercomputer based on the Six-Core AMD Opteron processor and features almost a quarter of a million cores. Additional Top 10 systems based on AMD technology are:

#3: Roadrunner, a hybrid system from IBM using AMD Opteron processors in conjunction with IBM Cell technology located at Los Alamos National Laboratory.
#4: Kraken, a Cray XT5 system at the University of Tennessee.
#7: Tianhe-1, a hybrid system using ATI Radeon™ graphics processors at the National SuperComputer Center in China.

Forty-seven additional AMD systems are in the TOP500 from OEMs including Appro, ClusterVision, Dawning, Dell, Fujitsu, Hitachi, HP, Koi Computers, Penguin Computing, and Sun.

“Our customers are selecting AMD platforms for supercomputing because they provide the cores, the memory, the power savings and clearly the performance that the world’s leading research institutions require for their ground-breaking work,” said John Fruehe, director, Server and Embedded product marketing at AMD.

“AMD has been a leader in delivering the benefits of x86 and open source computing to the HPC community and it will be exciting to see what further advances the AMD Fusion™ family of Accelerated Processing Units (APUs) will bring.”

Key facts
* The number of AMD technology-based Supercomputers on the TOP500 now stands at 51, a rise since November 2009.
* AMD technology helps drive more than 4.2 Petaflops of computing power on the TOP10 alone.
* Cray recently announced numerous new contracts for its next-generation Cray XE6 supercomputer to be based on AMD Opteron 6100 Series processors with the ability to scale to more than 1 million cores.
* In addition to universities and national labs, AMD also powers world-class supercomputing resources in the enterprise, including engineering, finance and IT service.
* AMD-based systems provide leading supercomputing resources across the globe including in the United States, China, Japan, the United Kingdom, Japan, Germany, Switzerland, Norway, and Finland.

Major shakeup in top 20 semiconductor ranking

SCOTTSDALE, USA: As discussed in detail in the May Update to The McClean Report, IC Insights has upgraded its forecasts for worldwide GDP, PC, and cellphone sales for 2010.

As a result, the global economic recovery and subsequent rebound in the electronic system and semiconductor markets has caused a significant re-alignment in the top 20 semiconductor company ranking (Fig. 1).

Fig. 1Source: IC Insights, USA.

The surging market for both NAND flash and DRAM is responsible for much of the shakeup in the ranking. As shown, Toshiba, Hynix, Micron, and Elpida all moved up at least one position in the top 20 list (Elpida jumped six spots). Although not moving up in the ranking, Samsung is on pace for at least a $30 billion semiconductor sales year in 2010! Moreover, IC Insights believes that Samsung could register as much as a 50 percent surge in sales in 2010.

The recent growth spurt by Samsung in the semiconductor market has spurred the company to plan a record amount of capital spending in 2010 for its semiconductor division ($9.6B). At this level of spending, Samsung would be responsible for 22 percent of the world's total semiconductor capital expenditures and would spend about as much as Intel and TSMC combined!

Although the Renesas and NEC merger (that created Renesas Electronics Corp.) was only official on April 1, 2010, in order to make future comparisons practical, the ranking in Fig. 1 combines the two companies' semiconductor sales for calendar year 2009 and 1Q10.

As shown, the combination of the two companies would have served to make the new entity the fourth-largest semiconductor company in the world in 2009. In 1Q10, the combined sales of the companies would have made it the sixth-largest company.

However, given the strong performance expected by TSMC in the foundry market this year, and the strong memory-driven growth expected to be posted by Hynix, IC Insights believes that Renesas Electronics will likely drop to the seventh position for all of 2010.

Some notable companies that fell in the ranking include Qualcomm, which slid from 8th to 12th, and Fujitsu, which fell from being ranked 19th in 2009 to 21st in 1Q10.

The first quarter of the year is always a seasonally slow one for the cellphone industry and IC Insights expects a significant rebound by Qualcomm in the second half of this year.

Fujitsu is undergoing a re-organization and streamlining of its semiconductor division and will likely stay just out of reach of the top 20 companies for the near future.

Source: IC Insights, USA.

Covidien announces agreement to sell Mallinckrodt Baker

USA & DUBLIN, IRELAND: Covidien, a leading global provider of healthcare products, recently announced a definitive agreement to sell its Specialty Chemicals business to an affiliate of New Mountain Capital, L.L.C. for a cash purchase price of $280 million.

Covidien's Specialty Chemicals business, headquartered in Phillipsburg, New Jersey, manufactures and markets high-purity chemicals and related products and services under two well-known and respected brand names, J.T.Baker and Mallinckrodt Laboratory Chemicals.

These products are widely used in research and quality control laboratories, microelectronics, environmental testing laboratories and universities, and for manufacturing in the pharmaceutical, biotechnology and other industrial markets.

TI showcases interactive Math Tools at 'Destination ImagiNation'

KNOXVILLE, USA: As tens of thousands of high school students gather here this week at Destination ImagiNation, they're getting a chance to compete head-to-head in a fun challenge of speed and trivia, while seeing first-hand the future of interactive math education.

Texas Instruments is organizing a competition at its Destination ImagiNation exhibit, pitting some of the country's brightest students against each other – and their teachers and parents - with Tom Reardon, a leading math educator and Texas Instruments Teachers Teaching with Technology (T3) instructor from Youngstown, Ohio, as moderator.

Participants will test their knowledge of education-related trivia in a game show-like contest using the latest TI-Nspire with Touchpad handheld learning device.

"These are some of the most talented and creative students from across the country, so it will be fun and more than challenging to see how well they do in these challenges," said Reardon. "More importantly, these students, their parents and teachers will see the latest trend in education, key technology tools that foster greater teacher/student interactivity in the math classroom."

The interactive and dynamic math classroom technology shown at this conference demonstrates how students' graphing calculator handhelds are networked in a classroom, using the TI-Nspire Navigator wireless classroom network system, to create a shared, real-time learning experience.

Teachers, for example, can send an exercise to each student's device while the entire class works on solutions together via projected screen images. Teachers can track student's individual progress, and replace pencil-and-paper quizzes with quizzes graded in real-time to make sure concepts are understood by the entire class, before moving onto the next part of the lesson. Students can also work in groups, via this in-class network, to foster shared learning.

The new TI-Nspire graphing calculator handheld is available through instructional dealers now and will be available at retail in time for back to school.

Saturday, May 29, 2010

iSuppli boosts Q1 semiconductor estimate; Renesas Electronics debuts in top-5

EL SEGUNDO, USA: Global semiconductor revenue in the first quarter rose by 2 percent compared to the fourth quarter, exceeding previous expectations, according to iSuppli Corp.

Semiconductor industry revenue in the first quarter amounted to $70.6 billion, up 2 percent from $69.2 billion in the fourth quarter. iSuppli’s previous estimate was for 1.1 percent compared to the fourth quarter of 2009.

Sequential revenue growth in the first quarter is a highly unusual event in the semiconductor industry. The first-quarter typically is a slower season of the year for chip sales compared even to the fourth quarter. The third quarter is typically the strongest quarter for sequential growth.

However, growth in the first quarter shows that the semiconductor industry is headed for a boom year in 2010.

“The first three months of 2010 delivered the fourth consecutive quarter of sequential growth in semiconductor revenues—the longest period of consecutive expansion in the industry since 2004,” said Dale Ford, senior vice president, market intelligence services, for iSuppli.

“Out of the more than 150 leading semiconductor suppliers tracked by iSuppli on a quarterly basis, only six saw their revenue decline in the first quarter of 2010 compared to the first quarter of 2009. Two-thirds of these suppliers were able to grow or maintain flat revenues from the fourth quarter of 2009 to the first quarter 2010. This represents a testament to the broad-based strength of the semiconductor industry recovery since the market hit bottom in early 2009.”

Among the world’s Top-10 semiconductor suppliers, six managed to expand their revenue in the first quarter of 2010 compared to the fourth quarter of 2009.

The table presents iSuppli’s ranking of the Top-10 semiconductor suppliers in the first quarter of 2010.Source: iSuppli, USA.

Ranking renaissance for Renesas
Newly-formed semiconductor supplier Renesas Electronics Corp. made a strong debut on the semiconductor Top 10 list in the first quarter, coming in at No. 5.

Renesas was formed from the merger of Renesas Technology and NEC Electronics and commenced business operations on April 1. The combined revenues of the two companies gave Renesas revenue of $2.9 billion and a market share of 4.1 percent in the first quarter of 2010.

“The creation of Renesas Electronics has resulted in the establishment of a market share powerhouse in the Microcontroller (MCU) market,” Ford said. “Prior to the merger, Renesas Technology and NEC Electronics were the No. 1 one and No. 2 suppliers of MCUs. As the No. 1 supplier of MCUs, Renesas Electronics in the first quarter generated more than 3.5 times the revenue of the next closest MCU supplier: Freescale Semiconductor.”

This kind of market share domination is surpassed in only two other segments of the semiconductor business: in microprocessors, with industry giant Intel Corp.—and in Digital Signal Processors (DSPs), with front-runner Texas Instruments Inc.

Renesas Electronics also places in the top rankings of a wide array of semiconductor markets tracked by iSuppli. The company in the first quarter ranked among the Top 10 suppliers in 13 separate market segments and sub segments. It also is ranked among the top five in eight segments: general purpose logic, display drivers, application specific logic, logic ASICs, analog ASICs, discrete components, radio frequency and microwave components and Small signal and other discretes.

Macro growth for Micron
The strongest performance among the Top 10 suppliers was posted by Micron Technology Inc., which achieved a stunning 14.1 percent increase in revenue in the first quarter to $1.8 billion, up from $1.6 billion in the fourth quarter.

Micron benefitted from strong revenue growth in DRAM. The DRAM market represented one of the hottest segments of the global semiconductor industry in the first quarter, with revenue rising by 8.8 percent to $9.4 billion, up from $8.7 billion in the fourth quarter.

On the opposite end of the scale was STMicroelectronics, suffered a 10 percent decline in revenue compared to the fourth quarter. However, STMicroelectronics’ revenues grew by more than 40 percent compared to the first quarter of 2009, which compares favorably to other non-memory suppliers among the top semiconductor makers.

Source: iSuppli, USA.

Wi-Fi IC shipments forecast to surpass 770 million units in 2010

SINGAPORE: Global shipments of Wi-Fi ICs have experienced an extraordinary growth in recent years, due to the increasing demands for wireless-enabled devices and enterprise level applications.

Wi-Fi IC shipments are forecast to surpass 770 million units in 2010, up almost 33 percent compared to 2009. Shipment of 802.11n ICs will surge ahead of 802.11g and dominate the market this year, accounting for approximately 60 percent of the total Wi-Fi IC shipments.

Growth engine
“The 802.11n standard which was ratified last year is a powerful growth engine to drive the Wi-Fi IC market increases,” says ABI Research wireless and semiconductor industry analyst Celia Bo.The accompanying chart shows the Wi-Fi IC shipment forecast by product type.

The cellular handsets segment is seen to be maintaining the highest unit shipment of Wi-Fi-enabled products in next five years, achieving an estimated CAGR of 25 percent between 2009 and 2015; the penetration rate will reach approximately 40 percent of the total handsets shipped in 2015.

Laptops, netbooks, and MIDs are other segments which will see higher shipments across all Wi-Fi-enabled products, and the trend will carry on throughout the following years.

Consumer electronics set the pace
“The penetration rate of Wi-Fi ICs in consumer electronic products will to grow continue robustly,” Bo continues. “Total shipments of consumer electronic products with Wi-Fi functionality are expected to exceed 530 million in 2015, with a 26 percent CAGR between 2009 and 2015.

“Shipments of Wi-Fi-enabled digital still cameras, TVs and DVD players will increase more than ten-fold in 2015 as compared to 2009. The demand for Wi-Fi-enabled home entertainment products such as networked game consoles and handheld game consoles is increasing as well: between 2009 and 2015, the CAGR will reach 8 percent and 6 percent, respectively.”

Mentor Graphics reports fiscal Q1 results

WILSONVILLE, USA: Mentor Graphics Corp. has announced results for the fiscal first quarter ending April 30, 2010. For the fiscal first quarter, the company reported revenues of $180.6 million, a non-GAAP loss per share of $.02, and a GAAP loss per share of $.22.

“While the quarter’s bookings were lower than last year due to the concentration of scheduled renewals in the second half of this year, the renewals that did occur in the first quarter were very strong, growing 25 percent from their prior contract values for the renewals within our top ten contracts,” said Walden C. Rhines, CEO and chairman of Mentor Graphics.

“Leading indicators that we have historically tracked were also very positive: support reinstatements grew 70 percent; our base business, orders less than $1 million typically from smaller customers, grew 20 percent over the year ago quarter; and consulting and training bookings grew 25 percent over last year.”

During the quarter, the company extended its customer partnerships with three significant new relationships. Mentor joined the Nano2012 program led by STMicroelectronics, in partnership with the French government, to develop leading-edge technologies for 32nm and below processes.

Freescale Semiconductor named Mentor Graphics its commercial Linux strategic partner. NetLogic Microsystems entered into a strategic collaboration with Mentor Graphics to provide multi-core multi-threaded Linux for their processors.

“Despite two sizeable acquisitions in the last year, our operating expense is still down on an absolute basis year on year. We expect our continued strong emphasis on cost controls, as well as an improving foreign exchange environment, particularly the Euro, positions us well for the year,” said Gregory K. Hinckley, president of Mentor Graphics.

“This fifth consecutive quarter of meeting or beating guidance, given our transparent real-time financial model, gives us confidence that the recovery is continuing.”

During the quarter, Mentor strengthened its offerings to the DO-254 market with a joint announcement of a product flow with The MathWorks, extensions to Mentor’s HDL Designer product to support DO-254 coding standards, and a new product, the ReqTracer tool, that helps automate requirements capture.

The company’s Mechanical Analysis Division launched FloTHERM IC for semiconductor package thermal characterization and design. Mentor launched 3D electromagnetic analysis for its HyperLynx PCB product line. The company completed its previously announced acquisition of Valor Computerized Systems which offers PCB manufacturing software and also acquired technology that provides on-demand electrical schematics for automobile dealerships.

In early May, Mentor launched its Calibre InRoute software, which fully integrates its Calibre tools into its Olympus-SoC place and route environment. This allows designers to invoke Calibre verification and design-for-manufacturing tools from within the place and route environment to verify and improve designs much faster, significantly speeding time to design closure.

In April, the Valor MSS Software suite won the Circuits Assembly New Product Introduction Award and the 2010 Surface Mount Technology Vision Award. Design News granted FloEFD mechanical analysis technology its Golden Mousetrap Award for Best Product.

In February, the International Engineering Consortium honored HyperLynx Power Integrity with its annual Design Vision Award in the System Modeling and Simulation Tool Category. Additionally, Mentor’s Dr. Vladimir Székely received the Dennis Gabor Award for Innovation, the country of Hungary’s highest technical honor.

For the fiscal second quarter ending July 31, 2010, the company expects revenues of about $180 million, non-GAAP earnings per share of break-even to a loss of $.05, and GAAP loss per share of $.17 to $.22.

For the full fiscal year 2011, the company expects revenues of $870 million, non-GAAP earnings per share of $.60 to $.65 and GAAP earnings per share of $.10 to $.15.

Magma reports revenue of $123.1 million for fiscal 2010

BANGALORE, INDIA: Magma Design Automation Inc. has reported revenue of $33.6 million for its fourth quarter and $123.1 million for its 2010 fiscal year, both ended May 2, 2010.

"Magma is in a much stronger position than a year ago, both in terms of products and financial performance," said Rajeev Madhavan, Magma chairman and chief executive officer. "Our key product groups - Talus, Titan, FineSim and Quartz - are demonstrating competitive strength and continuing to improve their traction in the market. As to our financial performance in fiscal 2010, we beat all guidance ranges and continued consistent cash generation. We are optimistic as we enter the new fiscal year."

GAAP results
In accordance with generally accepted accounting principles (GAAP), Magma reported a net loss of $(0.7) million, or $(0.01) per share (basic and diluted), for the fourth quarter, compared to a net loss of $(9.9) million, or $(0.21) per share (basic and diluted), for the year-ago fourth quarter. For fiscal 2010 Magma reported a GAAP net loss of $(3.3) million, or $(0.07) per share (basic and diluted), compared to a net loss of $(129.2) million, or $(2.89) per share (basic and diluted), for fiscal 2009.

Non-GAAP results
Magma's non-GAAP net income was $3.7 million for the quarter, or $0.07 per share (basic) and $0.06 per share (diluted), which compares to non-GAAP net income of $3.3 million, or $0.07 per share (basic and diluted), for the year-ago fourth quarter. For fiscal 2010 Magma's non-GAAP net income was $9.1 million, or $0.18 per share (basic) and $0.17 per share (diluted), compared to the company's non-GAAP net loss of $(6.5) million, or $(0.15) per share (basic and diluted), for the year-ago fiscal year.

In the fourth quarter Magma generated cash flow from operations of approximately $2.4 million.

Business outlook
For Magma's fiscal 2011 first quarter, ending August 1, 2010, the company expects total revenue in the range of $31.0 million to $31.5 million. GAAP net loss per share is expected to be in the range of $(0.07) to $(0.06) and non-GAAP earnings per share (EPS) are expected to be in the range of $0.02 to $0.03.

For Magma's fiscal 2011, ending May 1, 2011, the company expects total revenue in the range of $130.0 million to $133.0 million. GAAP net loss per share is expected to be in the range of $(0.16) to $(0.14) and non-GAAP earnings per share (EPS) are expected to be in the range of $0.18 to $0.20.

EB and Satimo unite their expertise in MIMO OTA testing

OULU, FINLAND & PARIS, FRANCE: EB (Elektrobit), a leading developer of cutting edge embedded technology solutions for wireless and automotive industries and SATIMO, a leader in electromagnetic field measurements in the microwave frequency range, have announced their partnership on MIMO Over-the-Air (OTA) testing.

The partnership combines the expertise of SATIMO and EB to offer a test solution that integrates the best performing technologies: multi-probe spherical measurement geometry, instantaneous calibration of the test system and high performance radio channel emulator.

"As the end-user performance requirements of new MIMO mobile devices constantly increase, it introduces new testing challenges for wireless device manufactures. We are glad to be able to provide a reliable and easy-to-use solution to the market together with our partner SATIMO" says Antti Sivula, senior vice president of EB's Wireless Communications Tools Business.

EB launched industry's first commercially available MIMO OTA emulator in February 2010. The EB Propsim F8 MIMO OTA emulator can produce signals in any geometry based channel model for a flexible number of probes.

The emulator is integrated in SATIMO's testing solution, together with a circular multi-probe arch, an instantaneous calibration unit, an amplification unit and a radio communication tester. This partnership provides a fully-operational MIMO OTA testing solution for the Telecom industry.

"The demand for such a solution has been growing strongly in the last few months. We are proud to offer thanks to this partnership a solution that perfectly fits the needs of wireless device manufacturers in terms of speed, performance and flexibility" tells Gianni Barone, sales director of SATIMO.

Friday, May 28, 2010

DRAMeXchange Compuforum 2010 to be held during Computex

TAIWAN: The DRAMeXchange Compuforum 2010 will take place on 1 June, 2010 (the first day of Computex Taipei) in Taipei International Convention Center.

DRAMeXchange will gather industry leaders from around the world to share their knowledge in the production, market trend and technical aspects of the memory and storage industry.

According to Joyce Yang, Vice President of DRAMeXchange Research Division of TrendForce Corp. will share her viewpoint on the ‘DRAM and NAND Flash Market View for 2010-2012’.

After loss was recorded in three consecutive years, DRAM vendors cut the capacity drastically in 4Q08. With the 8” fab phase out, total DRAM capacity had reduced 20% and DRAM vendors finally returned to the positive profit in 2009 with rebounding price. DRAM vendors initiated the 4nm migration in 2010.

However, 2010 DRAM supply growth still lies in uncertainty due to the difficulty in technology migration and immersion scanner shortage. Triggered by the recovering global economy and PC replacement effect, PC-OEMS shows the aggressive shipment perspective. NAND Flash rebounded from the bottom of 2009. Given the dynamics of iPad launch from Apple, the strong smartphone growth momentum, 3xnm/2xnm migration and rising TLC portion.
Dr. Antonio Mesquida Küsters, Director of Market Intelligence of ASML, will discuss on the issue ‘Advanced Lithography as key enabler of memory industry recovery’. Dr. Antonio Mesquida will present on the latest product roadmap and show why lithography-shrink is an economic and efficient way to increase bit-output next to the addition of new fab capacity or to the increase of bits/cell (in the case of NAND).

ASML calculates that a significant capacity ramp-up will be needed in the coming two years to properly address the expected demand, as a result of the next PC-upgrade cycle and the fast proliferation of smart phones, on top of a potential fast ramp-up of SSDs in notebook computers.

Dr. Alex Wang, President of Powerchip Semiconductor Corp., perceives that the DRAM outlook is bright since experiencing disastrous ten consecutive quarters of loss, the DRAM industry is back on track and returning to its glory days. Dr. Wang will focus his presentation on looking into the future and reviewing the past of the DRAM industry.

Joe Chen, General Manager of Zentel Electronics Corp., will enlighten Compuforum attendees with his speech on ‘Consumer DRAM’. DRAM is very widely used in various applications including not only computers but also digital consumer and communication devices.

Ranging from 16Mb through 1Gb, the DRAM for consumer applications typically have lower density but higher bandwidth than those for computers. SDR (Single data rate) and DDR (double data rate) are the most popular architectures, with DDR-2 emerging very quickly for the high performance video applications.

Doreet Oren, Marketing Director of SanDisk will be sharing her viewpoints on the ‘SSD Adoption and the Evolving Client PC’. Ms. Oren will focus on how the SSD’s multiple benefits enable a growing variety of Client PC devices. SSD manufactures must carefully tailor the specific needs for each usage model to best support the end user. SSDs need to meet different specs of performance, power consumption, and reliability and an assortment of form factors to address diverse needs.

Program Manager of Anobit, Yoav Kasorla will discuss on how Error Correction Code (ECC) is typically used to correct errors and retain reliability in NAND-based products and systems. A new technology termed Memory Signal Processing (MSP™) will be presented, which integrates advanced ECC with proprietary signal processing algorithms that compensate for NAND’s physical limitations.

Jet Huang, COO of JMicron Technology Corp., will reveal his viewpoints on how the next ten years will be an era of Cloud Computing. Everything will be computed in the Cloud. Therefore, Cloud needs more powerful servers and more quickly accessible storages. The characteristics of SSD and NAND Flash is high access rate and thin volume, which fits the need of Cloud Computing.

eTT (Effectively Tested) DRAM is being adopted in large volume by DRAM module manufacturers and computer system integraters for the benefits of price and availability. However there are concerns on eTT parts for shortcomings in quality and reliability due to its shortened or omitted test screening conditions.

Ukyo Jeng, Senior Director of A-DATA will examine on the difference in test conditions between eTT parts and fully finished parts, and demonstrates ways to achieve equivalent quality level of finished DRAM module using eTT parts.

Mentor Graphics Calibre co-development of TSMC’s iLVS simplifies modeling of advanced devices for physical verification

WILSONVILLE, USA: Mentor Graphics Corp. announced that the Calibre nmLVS product now provides comprehensive support for the iLVS interoperable rule specification used by TSMC for new design kits.

This allows customers to define and customize complex IC design rules, as needed, while maintaining compliance with TSMC specifications and allowing seamless adoption of EDA vendor performance optimizations.

The iLVS specification, which was co-developed by Mentor and TSMC, separates the rule definition syntax from underlying rule implementations. This allows Mentor to optimize the underlying implementation, reducing the need for users to tune the general rule specifications themselves.

Moreover, by using iLVS in conjunction with the Calibre nmLVS Advanced Device Properties (ADP) facility, the Calibre tool users can also establish modules for device building, enabling device model reuse and simplifying model customization for unique parameters. Previously, such customizations required manipulation of detailed SVRF scripts.

The iLVS syntax is one of two definitions jointly developed by TSMC and Mentor Graphics: iDRC, and iLVS—for describing physical verification and layout vs. schematic (LVS) rules. In addition, Mentor is also supporting TSMC’s iRCX syntax so mutual customers have a complete set of interoperable verification solutions from Mentor.

The definitions make it possible for TSMC and its customers to create verification decks that will work with the Mentor Calibre tool offerings as well as other verification products that support the specification. They also make it possible for Mentor to independently optimize the implementations to maintain performance to end users as the underlying process rules are updated by TSMC.

“The iDRC, iLVS and iRCX languages benefit both TSMC and its customers by making it possible to define and customize complex verification rules for each of our processes that can, in turn, drive verification tools from any supporting vendor,” said Tom Quan, director of EDA Alliances marketing at TSMC.

“This enables us and our customers to easily adapt design rules to new requirements or special situations without worrying about tuning and testing for different tool flows. We’ve worked closely with Mentor to co-define the architecture and syntax of these specifications and have completed validation on the Calibre tool suite as our lead implementation platform.”

“Our collaboration with TSMC on the definition of iDRC and iLVS, along with support of iRCX, makes it easier for our mutual customers to implement their own IP in TSMC decks and still maintain high performance and compliance with TSMC specifications,” said Michael Buehler-Garcia, director of Calibre Design Solutions Marketing at Mentor Graphics.

“With this collaboration, TSMC ensures their design guidelines are delivered in a consistent manner to all qualified vendors, and Mentor can use its proprietary technology to continue delivering industry leading verification platforms with the fastest and most efficient underlying code possible.”

The iDRC, iLVS and iRCX specifications are based on the open source TCL language extended with specialized functions for verification. They have been validated on the Calibre platform for 65nm and 40nm designs manufactured at TSMC, and will be rolled out as part of the TSMC reference flow for 28nm designs.

The Calibre implementation converts iDRC, iLVS and iRCX decks into highly-tuned native Calibre SVRF calls for optimum runtime performance. It also includes an interactive TCL debugger with breakpoints and variable monitors integrated with a layout debugger, which is part of the Calibre Results Viewing Environment (RVE), and a special in-line SVRF viewer.

MIPS and its ecosystem highlight solutions for next-generation SoCs

COMPUTEX TAIPEI, TAIWAN: MIPS Technologies Inc. has announced its program of events during COMPUTEX TAIPEI, being held June 1-5 at the Taipei World Trade Center (TWTC) and Taipei International Convention Center (TICC). During the show, MIPS Technologies will deliver multiple presentations in a range of forums, and will host an invitation-only event for customers.

"Last year during COMPUTEX, we announced availability of the Android platform on the MIPS architecture, and since that time, we've made incredible strides in our work with Android," said Art Swift, vice president of marketing, MIPS Technologies.

"This year we'll share the latest news on Android and other software platforms that are important for next-generation connected devices. We are also pleased to welcome key ecosystem companies and complementary IP providers to present their products and solutions that will help our customers develop compelling devices."

MIPS presentations
During the Cloud Computing Technology Forum, Art Swift will deliver a presentation, "Consumer Electronics: Innovation for Cloud Computing." The presentation will take place at 3:10 p.m. on May 31st in the TICC third floor ballroom.

During the DIGITIMES Mobile Technology and Design Forum, Kevin Kitagawa, MIPS director of strategic marketing, will present, "The Future of Mobile Devices in the Digital Home." The presentation will take place at 1:30 p.m. on Wednesday, June 2nd, in TICC Room 102.

MIPS Technologies Solutions Architect James Syu will deliver the presentation, "The Future Consumer Experience in an Android World," as part of the Taipei Computer Association Android Forum at 11:30 a.m. on Wednesday, June 2nd. The Forum will be held in TWTC Hall 1.

James Syu will also present during the Android Steps Ahead 2010/Taipei Conference at COMPUTEX. Sponsored by the Open Embedded Software Foundation (OESF), the event will be held in TICC Room 201A on Friday, June 4th from 1:30 p.m. - 5:30 p.m., with Mr. Syu's presentation at 3:00 p.m.

MIPS customer event
MIPS will host an invitation-only customer event during COMPUTEX, featuring several keynote presentations and demonstrations as well as a MIPS Ecosystem Pavilion. The event is sponsored by Adobe Systems, AllGo Systems, Cadence Design Systems, Chips&Media, Discretix, Home Jinni, Imagination Technologies, OESF, Sonics Inc., Tensilica and Viosoft Corp.

During the event, Art Swift will present, "Powering a Connected World" and Kevin Kitagawa, director of strategic marketing for MIPS Technologies, will present on key software platforms for the next generation of connected devices.

Keynote presentations include:

* "Bringing Flash to the Digital Home, " Brian Yang, Adobe Systems.
* "Embedded Graphics and GPUs: the Key to Multimedia Rich Product Success," Mike Hopkins, Imagination Technologies.
* "Security Platform for the MIPS Architecture Powered by Discretix CryptoCell," Baruch Toledano, Discretix.
* "Qt and MeeGo: Enabling a Connected World of Smart Devices," Tom Miller, Nokia.
* "Selecting the Right HD Video IP for Multimedia Applications," Phillip Han, Chips&Media.
* "Eliminating DRAM Performance Bottlenecks in Embedded SoCs," James Mac Hale, Sonics Inc.
* "Powering a Connected Word - Enabling Android Based Products," Art Lee, Viosoft Corp.

Product demonstrations during the event include:

* AllGo Embedded Systems will demonstrate its Android Application Extensions that bring key feature extensions to Android including uPnP/DLNA, DRM, third-party media player/components, media/protocol stacks, and more.
* Cadence Design Systems will share its new paper, "EDA360 - The Way Forward for Electronic Design." EDA360 is a new vision and call-to-action for the electronics industry to address a shift in focus from design creation to integration.
* Chips&Media will demonstrate its advanced video codec solution on an FPGA board with 16 CIF multi-channel and full HD (1920x1080p) multi-standard decoding such as H264, MPEG-4 and RMVB.
* Imagination Technologies will demonstrate the latest in advanced graphics and visual technologies for set-top boxes, mobile, computing and embedded, utilizing both current and prototype devices and the latest SoCs.
* OESF will demonstrate two MIPS-BasedTM Android set-top boxes-a prototype from KDDI R&D Labs and a new product from Covia.
* Sonics will demonstrate its latest on-chip network product, SNAPTM (Sonics Network for AMBA Protocol), which is now available for both Windows and Linux. Sonics will show SNAP's GUI-based evaluation environment that supports both homogeneous and heterogeneous multicore SoCs and provides a simple, yet powerful tool for capturing and analyzing on-chip bus designs.
* Viosoft will demonstrate its MIPS-Based Android porting and debug environment.
A range of MIPS licensees will showcase their products during COMPUTEX, including ALi Corp., Magic Pixel, Novatek, Ralink, Realtek, SiS and Trendchip.

ST expands SPEAr MPU family for high-performance apps

GENEVA, SWITZERLAND: STMicroelectronics has revealed the new architecture that will be the backbone for the new members of its popular SPEAr (Structured Processor Enhanced Architecture) family of embedded microprocessors, targeting high-performance connectivity and embedded applications.

Leveraging its experience of the production-proven SPEAr300 and SPEAr600 lines, the new SPEAr1300 product line couples powerful dual ARM Cortex-A9 processors with a DDR3 memory interface and is manufactured in ST's low-power 55nm HCMOS (high-speed CMOS) process technology. The dual ARM Cortex-A9 processors support fully symmetrical operation, at speeds up to 600MHz/core for 3000 DMIPS equivalent.

The SPEAr1300 makes use of ST's innovative Network-on-Chip technology for internal peripheral interconnect, assuring support for multiple different traffic profiles, while maximizing data throughput in the most cost-effective and power-efficient way. Initial sampling has already started to early adopters.

The new architecture offers industry-leading performance in terms of DMIPS/MHz and power consumption/DMIPS ratios, in addition to cost efficiency and customizability advantages.

The availability of integrated DDR3 memory controller and a full set of connectivity peripherals like PCIe, SATA, USB and Ethernet, among other features, make the SPEAr1300 the ideal choice for high-performance applications including networking, thin client, videoconferencing, NAS (Network-Attached Storage), computer peripherals, and factory automation.

"This new architecture for the SPEAr family builds upon the unrivalled low power and multiprocessing capabilities of the ARM Cortex-A9 processor core," said Loris Valenti, General Manager of ST's Computer Systems SoC Division. "Upcoming SPEAr embedded microprocessors will deliver an unprecedented combination of processing performance, memory throughput, flexibility and low power for next-generation connectivity appliances."

Key features of the new SPEAr1300 architecture include:
* Dual ARM Cortex-A9 cores, running at 600MHz for 3000 DMIPS equivalent.
* 64-bit AXI (AMBA3) bus Network-on-Chip technology.
* DRAM and L2 cache with Error Correction Code (ECC).
* 533MHz 32-bit DDR3 memory controllers with ECC; 16-bit DDR2 also supported.
* Accelerator coherence port.
* Gigabit Ethernet.
* PCIe 2.0 supporting 5 GT/s (Gigatransfers/second).
* SATA II 3 Gbit/s.
* USB 2.0.
* 256-bit key hardware encryption/decryption.
* 1.3 million gates of configurable logic.

Embedded microprocessors from the new SPEAr1300 product line will be announced over the next few months, expanding ST's SPEAr family and providing an extensive choice for leading customers.

TSMC announces 0.18-micron automotive grade embedded Flash IP

HSINCHU, TAIWAN: Taiwan Semiconductor Manufacturing Co. Ltd (TSMC) has announced the 0.18-micron automotive Embedded Flash IP as its second generation Embedded Flash IP that passed AEC-Q100 product qualification requirements for a wide range of automotive applications.

TSMC's 0.18-micron automotive Embedded Flash IP macro features 27 percent area reduction compared to an equivalent 0.25-micron Embedded Flash IP. The 0.18um technology generation hits a cost and performance sweet spot as vast amount of IPs have been developed for many applications.

The addition of this 0.18-micron automotive qualified Embedded Flash IP enables customers to extend their current 0.18-micron product portfolios to automotive micro-controller applications.

The 0.18-micron automotive Embedded Flash process entered initial volume production last year. More than 38000 8-inch wafers or an equivalent number of 43 Million automotive MCU units have been shipped. So far TSMC had observed lower failure rate as compared to the previous generation 0.25 um in which 0.1ppm or less has been achieved.

Much of the learning in bringing the 0.25-micron Embedded Flash technology to production readiness has also resulted in a quicker time in achieving this new record for the new IP.

Kuotung Cheng, director of automotive program at TSMC, said: "This new milestone results from a truly synergistic alignment between TSMC's strength in manufacturing consistency and our customers' expertise in test methodology. It underscores TSMC's relentless pursuit to meet the stringent automotive electronics requirements."

TSMC is the only foundry that provides AEC-Q100 qualified 0.25-micron and 0.18-micron Embedded Flash IP as general offers to all its customers.

Thursday, May 27, 2010

Tablet PC will be the spotlight during Computex 2010

TAIWAN: According to DRAMeXchange, strong netbook growth credit to the PC market in 2009 since netbook has featured with affordable price with performance. 2009 netbook shipment is recorded in 28 million units with 172 percent YoY growth.DRAMeXchange expects that netbook has reached the peak at 2009. With the declining ASP and low margin, PC-OEMs will re-focus on regular notebooks due to the preferred performance. The 2010 netbook market size is expected at 36 million units with 27.2 percent YoY growth.

Meanwhile, the Apple iPad, launched at April, is generally taken as the tablet PC. Many PC-OEMs will start to penetrate into tablet PC market given the shining iPad.

The tablet PC had been launched back to 2000 and targeted itself as the niche product. Due to the higher price, heavy weight, unsatisfactory battery endurance, lack back up for wireless and 3G connection, the tablet PC development is limited. The iPad has been positioned differently with the emphasis being more on friendly user interface, strong application and matured telecom support.

Apple believes that iPad will create a new space between smartphone and notebook. Compared with a million units sold in 74 days for iPhone, it took only less than a month for iPad to reach one million units sold. DRAMeXchange expects that the 1H10 iPad shipment should be around 1.7 million units while 7~8 million will be aimed for 2010 overall.

According to DRAMeXchange, the tablet PC is featured differently from netbook in fundamental. Consumers with higher demanded in office work will still prefer to use netbook as the computing device. However, users with higher demand in entertainment with internet browsing and simple tasking will choose tablet PC.

The iPad offers brand new using experience in terms of multi-touch and software/hardware application rather than netbook. We believe tablet PC will be more competitively advantaged with it can support multi-tasking and Flash player, which will result in the strong impact for competing with netbook.

Generally speaking, DRAMeXchange sees seldom overlapping customer base from netbook and tablet PC. That is, DRAMeXchange expects that the tablet PC will create another new market after netbook.

Intel, Asus and Acer will plan to launch and demonstrate the tablet PC products in Computex at this June. Also, Google will cooperate with Verizon on new tablet PC to compete with ipad. With the new joint and new structure that many companies are dedicating, tablet PC is expected to be another spotlight in PC world.

TSMC and co-development partners, Mentor and Synopsys, donate iDRC to Si2

AUSTIN, USA: Silicon Integration Initiative (Si2) announced that TSMC has donated iDRC, a vendor-neutral language for describing IC design rules, for consideration as an open industry standard.

iDRC is an open specification that makes it possible for TSMC and its customers to create physical verification design kits that allow easier support of physical verification products from different EDA vendors. TSMC has donated the iDRC specification to Si2, the organization of industry-leading silicon systems and EDA companies, on behalf of TSMC and its co-development partners, Mentor and Synopsys.

This donation culminates over two years of collaborative effort by the three companies to create an EDA vendor independent DRC mechanism that will enable faster adoption of vendor optimizations. To further support this effort, Mentor will be providing an architectural manual and sample implementations.

Synopsys has agreed to grant a RAND license for a related patent to Si2. Mentor and Synopsys will also be members of the Si2 committees that will help drive the adoption of this standard.

“The iDRC specification benefits our customers by accelerating the delivery of physical verification decks from TSMC, and once adopted as a standard, from other foundries as well,” said ST Juang, senior director of EDA and design service marketing at TSMC.

“iDRC also enables users to more easily create design rules for new requirements or special situations, while allowing individual EDA companies to implement rules in a manner that is optimized for their specific software. We’ve worked closely with Mentor and Synopsys to develop and validate iDRC architecture and decks for our most advanced processes. It was always our intent to donate this capability to the industry, and now that the concept is validated we are pleased to make this donation to Si2.”

“Our collaboration with TSMC on the definition of iDRC helps our mutual customers to obtain optimized design kits faster. By segmenting out process definitions from the software-specific implementations, iDRC simplifies the adoption of performance optimizations, allowing our joint customers to realize better performance from the Calibre platform,” said Joseph Sawicki, vice president and general manager for the Design-to-Silicon division at Mentor Graphics. “The donation of iDRC to the industry is another validation of Mentor’s support for open industry standards.”

“The collaboration with TSMC to transition from a vendor-specific to an iDRC-based interoperable specification will ensure timely distribution of optimized technology files. Function-based, vendor-independent DRC implementation eliminates qualification and consistency barriers, clearing the way to efficiently bring In-Design physical verification with IC Validator to our common customers,” said Antun Domic, senior vice president and general manager of Synopsys’ Implementation Group. “In support of open industry standards, we endorse this donation of iDRC to Si2.

“We are very excited about the donation of iDRC and the associated patent license from Synopsys for consideration as part of OpenDFM, not only as a specification, but also as a proven production solution,” said Steven Schulz, president and CEO of Si2.

“iDRC is consistent with the Si2 Design for Manufacturing Coalition’s (DFMC) OpenDFM vision, and is a great example of meeting industry challenges with open solutions developed through the collaboration of Si2’s member companies. Si2 will be reviewing the donation with Si2 members with the goal of formal acceptance within 30 days.”

StratEdge intros leadless, low-profile, hermetic, SMT packages

SAN DIEGO, USA: StratEdge, a leader in the design and production of semiconductor packages for microwave, millimeter-wave, and high speed digital devices, has introduced a new family of fully hermetic, low-profile, leadless surface mount (SMT) packages with improved electrical performance.

The SM family of packages fits aerospace, avionics, automotive, and telecom industry applications and is especially suited for LEDs, MEMS, and optical devices.

These new packages incorporate a metal plug in the base that allows a direct ground path for enhanced electrical performance. Anticipated performance is DC to 30+ GHz. The first package offered has a 5 x 5mm outer dimension and 28 I/Os. There are plans for other configurations including packages with 4 X 4mm, 6 x 6mm, and 8 x 8mm outer dimensions.

All SM packages meet stringent MIL-STD requirements for hermeticity. Additions to the SM Family will be offered as standard products, with samples and volume production quantities available in Q3 of this year.

The SM packages match industry-standard outlines enabling them to be used as direct replacements for traditional quad flat package designs. They can be used in place of plastic over-molded packages in applications where an air cavity is desired.

The air cavity provides improved microwave performance, allows for ease of rework and repair, and is ideal for prototyping. In addition, air cavities are often necessary for sensors and other devices that need to respond to movement.

Tim Going, StratEdge president, said, “StratEdge’s new SM packages give designers an alternative to plastic over-molded packages, enable them to get superior electrical performance, and are cost effective because of the ease of repair and rework.”

5 GHz differential amplifier drives gigasample ADCs on 60 mA of quiescent current

NORWOOD, USA: Analog Devices Inc. (ADI) has introduced the industry’s first 5-GHz differential amplifier able to drive ADC (analog-to-digital converter) signals from DC to 1 GHz at half the power of competing products.

The ADA4960-1 differential amplifier is a high-performance, low-distortion, ultra-high-speed differential amplifier effective for a wide variety of high-speed ADCs with 10-bit linearity to 500 MHz and 8-bit linearity up to 1 GHz. The ADA4960-1 differential amplifier can drive a wide variety of ADCs, such as Analog Devices’ AD9626 12-bit ADC and the AD9211 10-bit ADC.

The ADA4960-1 differential amplifier (data sheet) consumes just 60 mA of quiescent current when operating up to 1 GHz. The amplifier features a 8,700 V/μs (volts per microsecond) slew rate (AV = 6 dB, 2-V step) and wideband, low-distortion performance for frequencies up to and beyond 1 GHz, which make it effective for RF (radio frequency) and IF (immediate frequency) wired communications applications in industrial and instrumentation, defense electronics and aerospace designs.

The user accessible gain adjust and bandwidth extension features allow configuration of the ADA4960-1 for line driver and channel equalization applications.

Semtech, Virtual Extension to bring new generation of wireless mesh networks to smart lighting apps

CAMARILLO, USA: Semtech Corp., a leading supplier of analog and mixed-signal semiconductors, and Virtual Extension (Tel Aviv, Israel), a leading mesh wireless sensor network provider, announced a two-chip wireless mesh network chipset that brings a new level of performance and signal robustness to smart lighting applications.

The chipset pairs Semtech’s SX1211 transceiver for industrial, scientific and medical (ISM) band applications with Virtual Extension’s VE209S wireless mesh controller.

Smart lighting designers now have a low-power, high-performance solution for building a wireless sensing network with no single point of failure and very robust signal processing. This low-power chipset is also perfectly adapted to battery-operated applications with a 10-year operating lifetime.

The SX1211 is part of Semtech’s complete platform of ISM-band transceivers and is optimized for asynchronous sensor network designs in unlicensed ISM frequency bands (868-870 MHz and 902-928 MHz).

The device features the industry’s lowest receiver current consumption (<3mA) for increased battery life. All of the transceiver’s major RF communication parameters are programmable and can be configured dynamically, with RF output power programmable up to +12.5 dBm.

The VE209 family of high-performance mesh controllers serves as the main building blocks of a VEmesh unit, either a gateway or a node. These mesh controllers have the necessary internal elements for performing all the interfaces and network management.

VEmesh units provide highly reliable bi-directional communication and best-in-class range and coverage for distributed monitoring and data collection of sensor and metering systems.

All VEmesh nodes also act as relays to retransmit data from other units in order to create a modular solution with no practical limitation to the number of nodes or size of coverage area.

“This new chipset is great news to smart lighting designers, who now have now a highly reliable network that also has great potential for additional applications, such as smart metering or home and building automation,” said Sameer Vuyyuru, Semtech Vice President Marketing for Semtech’s Advanced Communications and Sensing Group.

“The relationship with Virtual Extension means we can offer good integration between two of the industry’s highest performing ICs, and comes at the right time for Semtech to expand its leadership in these times of growing focus on energy efficiency.”

“Until now, the market has not had a mesh option that offers the winning combination of high performance, low power consumption and low cost,” said Yariv Oren, CEO of Virtual Extension.

“Semtech brings the high-performance transceivers that, when combined with our ‘diversity path mesh’ technology, results in networks that are easier to design and build, are much more robust, easier to install and maintain, and have higher scalability. This chipset offers a simple, low-power, robust routing solution for wireless mesh networks.”

Freescale furthers embedded development capabilities by adding five advanced Tower System modules

AUSTIN, USA: Freescale Semiconductor continues to enable advanced development through rapid evaluation and prototyping with its Tower System development platform. The company announced two processor modules, three interchangeable peripheral modules and a number of partner-developed modules for the reconfigurable development platform.

The processor modules are specific for industrial networking, automotive, human-machine-interface and portable handheld and metering applications. The peripheral modules offer graphical LCD, serial memory and capacitive touch functionality, allowing for the development of highly advanced microcontrollers, with the same ease-of-use and customization features already inherent in the Tower System.

The Tower System provides a customizable embedded design environment that allows developers to mix and match processor and peripheral boards to create reconfigurable development platforms that suit their design needs.

Interchangeable modules promote reuse of hardware across multiple architectures, which helps speed time to market. The modular design scales down overall tool costs, while providing an inexpensive entry point.

Advanced microcontroller and microprocessor modules
* The MPC5125 module (TWR-MPC5125) is one of the first microprocessor modules available as part of the Tower System. Designed for industrial networking, automotive, and human-machine-interface (HMI) solutions, the TWR-MPC5125 module features HDMI, USB2.0 OTG, Ethernet, microphone, and stereo audio output and can serve as a single-board computer.

* The MC9S08LH64 module (TWR-S08LH64) features the ultra low power MC9S08LH64 segment LCD controller with integrated 16 bit ADC, providing the user with development hardware for portable handheld and entry-level metering applications.

These modules compliment the previously announced MCF52259 V2 ColdFire connectivity module (TWR-MCF5225X), the MCF51CN128 V1 ColdFire Ethernet module (TWR-MCF51CN), and the MC9S08LL64 8-bit segment LCD module (TWR-S08LL64).

In future months, Freescale and its partners plan to provide Tower System support for additional embedded devices, including other ColdFire MCUs, 8-bit MCUs and digital signal controllers (DSCs).

Peripheral modules
* The LCD module (TWR-LCD) adds graphical LCD functionality with a 3.2-inch QVGA display, touch panel, integrated display controller and frame buffer.

* The Memory module (TWR-MEM) enables Serial Flash, MRAM, SD Card and Compact Flash interface functionality.

* The Swappable Sensor module (TWR-SENSOR-PAK) provides capacitive touch, accelerometer, barometer, pressure, ambient light and temperature controls.

These three modules complement the previously announced peripheral modules, including the serial module, (TWR-SER), which supports Ethernet, USB, RS232, RS485 and CAN; the elevator modules (TWR-ELEV) that connect the processor and peripheral boards; and the prototyping module (TWR-PROTO), which allows for custom circuitry design.

Partner module development
Complimenting a growing portfolio of Tower System modules from Freescale are a number of partner-developed modules. New to the Tower System are:

* StackableUSB I/O Device Carrier module from Micro/sys – enabling additional expansion of the Tower System with StackableUSB I/O devices.
* i.MX515 ARM Cortex-A8 Tower Computer Module from Micro/sys – featuring ARM Cortex-A8 processor, 800MHz, SDRAM, Flash, USB, Ethernet, Controller Area Network (CAN), serial ports, SD/MMC card slot and 16 bits of digital I/O.
* Rapid Prototyping System (RPS) FM1 module from iMn MicroControl – providing simple hardware and software modular prototyping and reconfiguration capabilities within and across Freescale processor families without incurring software programming changes.
* Rapid Prototyping System (RPS) AM1 module from iMn MicroControl – used to prototype hardware designs using Surface Mount Device (SMD) and through hole components.

The Tower System
The Tower System helps developers quickly evaluate and prototype their applications. As they require more functionality and design capabilities, developers can easily add more modules to their Tower System library.

In addition, standardized, open-source hardware allows Freescale customers and partners to design additional modules for added functionality and customization.

The TWR-MPC5125 module is available for a suggested resale price of $119. The TWR-MPC5125-KIT includes the TWR-SER and TWR-ELEV modules and is available for a suggested resale price of $169.

The TWR-S08LH64 module is available for a suggested resale price of $69. The TWR-S08LH64-KIT includes the TWR-PROTO and TWR-ELEV modules and is available for a suggested resale price of $99.

The TWR-LCD module is available for a suggested resale price of $99. The TWR-MEM module is available for a suggested resale price of $89. The TWR-SENSOR-PAK module is available for a suggested resale price of $149.

CSR SiRFatlasV boosts integration, performance for consumer navigation systems

TAIPEI, TAIWAN: CSR announced the SiRFatlasV multifunction GPS system processor, a next-generation system-on-chip device with higher levels of integration, performance and cost-effectiveness that enables manufacturers to create high-volume, value-priced consumer navigation and location-aware products.

Available now in production quantities, SiRFatlasV’s ARM 11 and DSP dual-core architecture delivers high performance GPS, high-MIPs application computing and robust multifunction capabilities on a single chip to reduce system cost and size while speeding time to market.

“SiRFatlasV is the next step in the evolution of our mainstream navigation platform, bringing even greater functionality on chip and delivering faster fixes and higher performance than ever before while reducing overall power consumption, system cost and size,” said Kanwar Chadha, chief marketing officer at CSR.

“All of this plus the considerable time-to-market advantages of our Synergy connectivity solution make SiRFatlasV the platform of choice for a new generation of mainstream PND and location-aware consumer devices.”

The SiRFatlasV processor combines on a single chip a 500- or 664-MHz ARM11 processor core with vector floating point unit; advanced, autonomous GPS/Galileo baseband DSP core with available SiRFAlwaysFix technology, DDR2, Mobile DDR, SD/MMC/MMC+ and NAND flash memory controllers; audio DAC; LCD touch panel controller, video post processing accelerator; USB 2.0 and other connectivity interfaces and a complete power management unit.

This high degree of integration reduces parts count and bill of material (BOM) costs, power requirements and PC board size while simplifying design and speeding development and time to market.

“Microsoft is excited to be working with CSR to deliver rich, specialized application experiences on the SiRFatlasV navigation platform,” said Kim Chau, senior partner manager for Windows Embedded at Microsoft Corp. “With SiRFatlasV, CSR has created an optimized and developer-friendly Windows Embedded CE 6.0 platform for mobile navigation, and we look forward to working with CSR to continue to drive innovation and differentiation in this market.”

Windows Embedded CE 6.0 is a componentized, real-time operating system that delivers compelling experiences on a wide range of small footprint consumer and enterprise devices. By building on the high performance and highly reliable Windows Embedded CE platform, device makers can bring their device to market quickly and efficiently.

“We are very pleased with the customer and partner response to SiRFatlasV,” said Ahmet Alpdemir, senior vice president for the Automotive/PND business unit of CSR. “AtlasV is already in use by a number of leading original equipment and original device manufacturers, including GlobalSat Technology Corporation, Mango Research Corp., Mobile Devices, Topicon HK Limited and YF International Limited.”

Using CSR Synergy, the SiRFatlasV processor can be seamlessly integrated with CSR’s audio and connectivity platforms incorporating a broad range of technologies – Bluetooth, Bluetooth low energy, Wi-Fi, echo cancellation, noise suppression, FM receive and transmit and more.

CSR Synergy ensures that all of these systems work together as a unified platform, enabling technologies such as Bluetooth and Wi-Fi to coexist in the same system environment without interfering with one another or degrading performance. This simplifies design engineering and helps achieve an overall improvement in the end-user experience.

Northrop Grumman doubles frequency of fastest reported IC

REDONDO BEACH, USA: Northrop Grumman Corporation (NYSE:NOC) has set a new electronics performance record with a Terahertz Monolithic Integrated Circuit (TMIC) operating at 0.67 terahertz (THz), or 0.67 trillion cycles per second.

Developed at the company's Simon Ramo Microelectronics Center under a contract with the Defense Advanced Research Projects Agency's (DARPA) Terahertz Electronics program, this new performance record more than doubles the frequency of the fastest reported integrated circuit.

Dr. William Deal, THz Electronics program manager for Northrop Grumman's Aerospace Systems sector, detailed the performance of this new TMIC amplifier today at the Institute of Electrical and Electronics Engineers' (IEEE) International Microwave Symposium being held in Anaheim, Calif. He told fellow scientists that the TMIC amplifier is the first of its kind operating at 670 GHz.

He said: "A variety of applications exist at these frequencies. These devices could double the bandwidth, or information carrying capacity, for future military communications networks. TMIC amplifiers will enable more sensitive radar and produce sensors with highly improved resolution."

The goal of DARPA's Terahertz Electronics program is to develop the critical device and integration technologies necessary to realize compact, high-performance, electronic circuits that operate at center frequencies exceeding 1.0 THz. Managed by DARPA's Microsystems Technology Office, the program focuses on two areas – terahertz high-power amplifier modules, and terahertz transistor electronics.

According to Dr. John Albrecht, THz Electronics program manager for DARPA, "The success of the THz Electronics program will lead to revolutionary applications such as THz imaging systems, sub-mm-wave ultra-wideband ultra-high-capacity communication links, and sub-mm-wave single-chip widely-tunable synthesizers for explosive detection spectroscopy."

A transistor amplifier magnifies input signals to yield a significantly larger output signal. In 2007, Northrop Grumman set a new world record for transistor speed with an ultra-fast device to provide much higher frequency and bandwidth capabilities for future military communications, radar and intelligence applications.

The company produced and demonstrated an indium phosphide-based High Electron Mobility Transistor (InP HEMT) with a maximum frequency of operation of more than 1,000 gigahertz, or greater than one terahertz.

Cypress and BITS Pilani - K.K. Birla Goa Campus team up on new PSoC 3 lab

BANGALORE, INDIA: Cypress Semiconductor Corp. and the Birla Institute of Technology and Science (BITS), Pilani - K.K. Birla Goa Campus (BPKKBGC) signed a memorandum of understanding for collaborative research and funded lab development based on the PSoC 3 programmable system-on-chip. The MoU was signed by Prof. K.E. Raman, Director, BPKKBGC and Patrick Kane, Director of Cypress University Alliance.

Patrick Kane visited the campus where he inaugurated a state-of-the-art PSoC 3 lab—the first of its kind in India. The lab will expose students to the PSoC platform, a flexible family of devices with programmable analog and digital blocks integrated with a microcontroller. With its unique architecture, PSoC provides an unrivaled learning platform for embedded design students and will enable them to create projects and solutions for embedded systems.

“Our focus is to excite students about new technologies and hence grow the pool of budding, talented engineers from India. The PSoC lab will allow students to innovate and work on high-tech projects,” said Patrick Kane. He and his team interacted extensively with both students and faculty at BPKKBGC. They also conducted a workshop for the Electrical, Electronics and Instrumentation Group.

“The lab has added an extra dimension to the student learning experience and has resulted in a unique learning platform where students now receive real-world, hands-on experience in developing applications,” said Prof. Raman.

Students from BPKKBGC have implemented a number of projects using PSoC 1 technology. Some of these include a BLDC motor driver, a pH meter, an accelerometer based tilt sensor, a PWM driven hexapod etc. These projects are currently being developed using the new PSoC 3 platform, which uses an 8051 core as well a programmable analog and digital modules.

Students have also been involved in research based projects such as study of battery charging algorithms using the PSoC. They have also assisted Cypress in development of the Power Line Communication solution. A PSoC 3 manual by BITS Goa is also in the pipeline.

Mercury Computer Systems enables scalable, cost-effective solutions with MicroTCA platform

CHELMSFORD, USA: Mercury Computer Systems Inc., a leading provider of open, embedded, high-performance computing systems, software, and services for image, sensor, and signal processing applications, announced a systems-level enhancement for solutions based on the MicroTCA standard.

The new, innovative six-slot chassis is part of Mercury’s Ensemble 2000 MicroTCA Platform, a standards-based solution built around the power, functionality, and scalability of RapidIO, Ethernet, IPMI, AdvancedMC, and MicroTCA industry standards.

Switches are built into the chassis backplane to support both Gigabit Ethernet (base interface) and a choice of communications fabrics including RapidIO, 10 Gigabit Ethernet, and PCI Express. The backplane also includes built-in system manager functionality. This built-in functionality means that a separate MCH module is not required, reducing costs and allowing all slots to be configured with AMCs.

“Designers of sophisticated industrial equipment, in industries such as Communications and Semiconductor Manufacturing, need high-performance, high-bandwidth embedded computing in cost-effective packages,” said Steve McPherson, Director of Business Development at Mercury. “With its compact size, scalability, and integrated system functionality, our new six-slot MicroTCA chassis provides a flexible platform for building those types of solutions.”

The new Ensemble 2000 chassis is also appropriate for a wide range of system sizes, with multi-chassis scalability built into the design. It supports mechanical stacking in a 19-inch rack; and the base interface, fabric interface, and clock can all be daisy-chained across multiple chassis.

Robust system configurations are also supported by Mercury’s industry-leading family of processor AMCs, including Xilinx FPGAs, TI DSPs, PowerQUICC, Power Architecture MPC 8641D, and Intel Penryn processors.

Docea announces power and thermal modeling and analysis capabilities for Aceplorer, previews AcePowerModeler

MOIRANS-GRENOBLE, FRANCE: Docea Power, the design-for-low-power company that delivers software solutions for power and thermal analysis at the architectural level, today announced a new version of its system-level power and thermal modeling platform: Aceplorer 2.0.

The new version adds project management capabilities to boost productivity and a link to virtual platforms to assess the impact of complex scenarios and embedded software on a system’s power consumption.

At the 47th Design Automation Conference (DAC) next month, Docea will preview AcePowerModeler, a power model generator tool that closes the loop between implementation and architectural modeling by automating the creation of power models from lower level simulation and characterization data.

Two main challenges face system architects for power simulation at a high abstraction level:
* How to describe the activity and capture a realistic scenario for the architecture, and
* Where to get power models to describe the architecture.

Aceplorer 2.0 answers the first challenge by linking to virtual platforms to allow the import of traces describing the activity in standard VCD (Value Change Dump) format. With new platforms and systems-on-chip embedding more and more functions and software, the complexity of use cases and use scenarios is exploding.

With this link, architects can continue to optimize the performance of their designs on their current flow, and have the possibility to measure the impact of complex scenarios and embedded software on the power consumption of their design’s architecture. Since the VCD output format is a standard, Aceplorer can now be used in combination with any performance analysis flow.

As for the second challenge, Ghislain Kaiser, CEO, Docea Power, noted: “In most design projects, around 80 percent of the blocks are reused with some variation from previous designs. Within these legacy designs, there is a tremendous amount of data from power simulations at the gate level or from netlists and from measurements. It can take hours of simulations and testbench setups to extract this data, and now with Aceplorer 2.0 it can be exploited by system architects.”

AcePowerModeler automates the generation of power models from power figures and tables extracted from low level descriptions and from measurements. These models can be re-used by architects at a higher abstraction level for much faster simulations allowing architectural exploration and optimization with no loss of accuracy.

Aceplorer 2.0 is available now. AcePowerModeler is available now for select customers, and will be released in Q4. It can be used with Aceplorer or stand alone.

UMC uses Silicon Frontline’s Field Solver to generate reference extraction data

LOS GATOS, USA: Silicon Frontline Technology Inc. (SFT) announced that its 3D extraction software for post-layout verification F3D (Fast 3D) has been qualified by United Microelectronics Corp. (UMC), a leading global semiconductor foundry, as the reference field solver for parasitic extraction.

UMC verified F3D’s accuracy through extensive comparison with internal benchmarks. The reliability and repeatability of results led to UMC’s adoption of F3D to generate reference data. Silicon Frontline’s F3D provides field solver accuracy for full-chip design, enabling higher quality extraction and faster post-layout verification closure.

“We are excited to add F3D as another reference field solver at UMC. We adopted Silicon Frontline’s F3D as a 3D extractor because it provides accuracy for many styles of circuitry, including high precision analog such as ADCs,” said Stephen Fu, Director of IP Development and Design Support at UMC. “This opens the door to providing higher quality silicon to customers.”

“Having UMC, a leading and well-respected silicon foundry, select F3D for generating reference parasitic extraction data boosts customers’ confidence in our results,” added Yuri Feinberg, Silicon Frontline CEO. “As customers experience F3D’s ability to accurately match sensitive parasitics, they realize more aggressive design goals are achievable and accurate design verification is possible.”

Silicon Frontline’s post-layout verification software guarantees accuracy and high performance by using rigorous 3D technology to extract parasitics. Users have the option to specify the level of accuracy desired, net by net, at the block level or with regular expressions. By guaranteeing accuracy, Silicon Frontline is ensuring the resulting parasitics are correct within the user-specified accuracy.

In July 2009, UMC validated F3D for its nanometer design processes.

Graphene Laboratories, CVD Equipment in exclusive distribution agreement for CVD Graphene products

RONKONKOMA, USA: CVD Equipment Corp. has signed an exclusive distribution agreement with Graphene Laboratories Inc. for Chemical Vapor Deposited (CVD) Graphene products.

Under this Agreement CVD Equipment Corporation will manufacture CVD grown Graphene based materials and products and Graphene Laboratories, Inc. will market and sell them on a worldwide basis.

CVD Equipment’s Application Laboratory provides process development and material growth services for a wide range of advanced nanomaterials, i.e., Carbon Nanotubes, Silicon and other Nanowires, CVD Graphene, Transparent Conducting Oxide (TCO) materials and other CVD processes. It hosts a range of CVD research and production equipment that will be utilized for CVD Graphene production.

Graphene is a novel nanomaterial carbon film that is only a few atoms thick and possesses unparalleled electrical and mechanical properties as well as supreme stability and durability.

CVD grown Graphene is projected to be used for production of Graphene-based electronics, sensors, MEMS, solar batteries, etc. Some of the CVD Graphene products sold by Graphene Laboratories Inc. will be marked with one or more trademarks from CVD Equipment, such as nMEMStarter, nFoil, and CVDGraphene.

“The ability to mass produce CVD Graphene is a key milestone for Graphene commercialization,” said Dr. Elena Polyakova, CEO of Graphene Laboratories.

“Currently, the progress in development of Graphene-based commercial products is largely stalled by a lack of supply of high-quality wafer-size Graphene films. CVD grown Graphene is well positioned to address this market demand. We anticipate strong interest from academic and industrial customers in our CVD Graphene products and this is an extremely important partnership for our Company. By selecting CVD Equipment Corporation as our partner, we will be able to expand our Graphene based product offerings and greatly advance the development of various Graphene enabled products.”

"CVD Equipment is focusing on enabling the commercialization of tomorrow’s technologies,” says Karlheinz Strobl, VP of Business Development of CVD Equipment.

“By leveraging the process development and manufacturing capabilities of our Application Laboratory and by collaborating with Graphene Laboratories Inc. on CVD Graphene based product developments, we believe we can shorten the time to market for a range of already existing and future nano enabled products. Together, we are able to offer and ship a growing array of CVD Graphene products. Our initial product variety has already been supplied to our first customers.

JDSU adds one-way delay test feature to T-BERD(R)/MTS-6000A

MILPITAS, USA: JDSU introduced the first field-portable solution for "one-way delay" testing. An enhancement to the T-BERD/MTS-6000A Multi-Services Application Module (MSAM), the solution provides measurement accuracy 10 times greater than most service level agreements (SLAs) currently require for Ethernet Backhaul and mission-critical applications.

This new feature helps to measure and troubleshoot service delay in networks that carry real-time voice, video and data services in Ethernet backhaul applications, as well as services in government and financial networks.

The JDSU One-Way Delay test feature enables providers to measure the delay of Ethernet, Internet Protocol version 4 (IPv4) and IPv6 traffic. This is critical for industries with real-time applications such as Voice over IP (VOIP), in which delay causes unacceptable quality issues, and financial transactions that depend on nearly instantaneous transmissions.

"One-way delay is a common factor in the degradation of voice, video and data service quality and reliability," said Mirna Mekic, director in JDSU's Communications Test and Measurement business segment.

"The JDSU One-Way Delay test feature for the T-BERD/MTS-6000A MSAM gives those responsible for network operations a simple and accurate method to perform a critical one-way SLA delay measurement that can characterize network performance. This unique feature provides valuable information useful in network turn-up and troubleshooting so that carriers can assure SLAs and optimize their networks to enhance quality of service."

JDSU's T-BERD/MTS-6000A MSAM is the industry's most compact multi-function tester. It supports the installation and maintenance of Carrier Ethernet and Internet Protocol (IP) services while also having the ability to simultaneously test Fiber Channel, Optical Transport Network (OTN), NextGen, Synchronous Optical Network (SONET/SDH) and legacy Time Division Multiplex (TDM) protocols all in one rugged, handheld unit.

Infineon and Elpida settle legal dispute

NEUBIBERG, GERMANY: Infineon Technologies AG recently announced that it has settled its patent infringement claim against Elpida Memory Inc., and both Infineon and Elpida have agreed to seek dismissal of all pending patent infringement cases.

Infineon initiated proceedings in February 2010, when it filed a complaint against Elpida and Elpida’s customers in the US International Trade Commission (ITC). Elpida subsequently filed two lawsuits in the US District Court, Eastern District of Virginia.

Infineon and Elpida have settled the dispute through a broad patent cross license relating to semiconductor technology. The specific terms and conditions of the license are confidential.

“Infineon is pleased to have reached this agreement with Elpida, and we look forward to a lasting peace between the companies,” said Prof. Dr. Hermann Eul, Member of the Management Board, responsible for Sales, Marketing, Technology and R&D at Infineon Technologies AG. “This outcome is further affirmation of our ongoing efforts to protect our intellectual property rights and business interests.”

Oclaro accelerates 100 Gbps coherent product development through alliance with ClariPhy

SAN JOSE, USA: Oclaro Inc., a tier-one provider of innovative optical communications and laser solutions, announced it has made a $7.5 million strategic investment in ClariPhy Communications, a privately-held fabless semiconductor company focused on digital signal processing (DSP) and mixed-signal integrated circuits (ICs) for high-speed next-generation networks.

In addition, ClariPhy and Oclaro have signed a Co-Marketing and Development Agreement leveraging ClariPhy's industry-leading 40nm, single-chip products with Oclaro's optical technology. The alliance with ClariPhy is an important milestone in Oclaro's strategy to build upon its leadership position in 40 Gigabits per second regional and metro networks and expand into the 100 Gb/s Coherent long-haul and ultra-long-haul markets.

The surge in new broadband services, such as social networking, video sharing, voice over IP (VoIP) and cloud computing, is creating significant demand for increased bandwidth and improved network performance, with global IP traffic expected to grow at a 40 percent CAGR between 2008 and 2013.

This intensive growth is driving the rapid transition from 10 Gb/s optical networks to 40 Gb/s and beyond. These very high bit rate communications require not only advanced optical solutions but also advanced DSP and mixed-signal integrated circuits, combined into modules for deployment by telecommunications systems providers. In particular, the move to 100 Gb/s requires Coherent technology, which is fundamental to extending the reach of high-speed networks.

"We expect an increasing percentage of the transceiver solutions for optical networks to be comprised of DSP and mixed-signal electronics as they evolve towards 40 Gb/s and 100 Gb/s," stated Alain Couder, President and CEO, Oclaro.

"Through our investment and alliance with ClariPhy, Oclaro believes it will be able to offer its customers best-in-class electronics and optical technology as a complete solution from a single source, whether incorporated directly in our Oclaro solutions, or co-marketed as complementary products."

Oclaro is a market leader in the 40 Gb/s market, with a leading market-share position in regional and metro networks. In the Differential Quadrature Phase Shift Keying (DQPSK) and Differential Phase Shift Keying (DPSK) space for regional and first-generation long-haul markets respectively, Oclaro already offers Lithium Niobate (LiNbO3) and Indium Phosphide (InP) component solutions.

At the sub-system level, the Oclaro vertical-integration model has resulted in ground-breaking technology disruption, as demonstrated by Oclaro's fully-qualified 40 Gb/s DQPSK 300-pin transponder solution for regional and metro applications. From this base, Oclaro is now looking to broaden its high bit rate portfolio into next-generation long-haul and ultra-long haul with coherent detection methodology.

With the standardization of 100 Gb/s gaining momentum, Oclaro believes it will continue to deliver these core optical building blocks, alongside ClariPhy's world-class signal processing engines, and to provide best-in-class module solutions.

"By leveraging the significant 40nm CMOS technology innovation from ClariPhy, Oclaro will focus on optimizing our future optical products to further increase bandwidth, improve network performance, and lower the total cost of ownership for customers," added Couder.

Oclaro and ClariPhy have a history of collaboration and offer products that have been designed to improve the performance and bandwidth of optical networks. With an industry-leading low power dissipation, Oclaro's TL9000M small form factor 300-pin transponder for 10 Gb/s networks, announced in 2009 and containing ClariPhy's maximum likelihood sequence estimation (MLSE) IC, established a new benchmark in transmission performance for dispersion-tolerant modules.

Oclaro's 300-pin transponder portfolio continues to ramp and take market share in the 10 Gb/s space. Oclaro is now taking this to the next level by driving a product strategy to deliver technology-disruptive transceivers such as Tunable XFP and XFP+, which when combined with ClariPhy's IC, is believed to deliver the industry's highest-density, lowest-power MLSE-based solution.

Oclaro and ClariPhy believe that the ongoing combination of the companies' advanced optics and signal processing delivers the performance and integration the market demands for these next generation 10 Gb/s modules.

"We are delighted to enter into a strategic alliance with Oclaro," said Dr. Paul Voois, co-founder and CEO of ClariPhy. "This alliance brings together industry-leading mixed-signal CMOS technology from ClariPhy with the world-class optical technology from Oclaro. By working together to deliver innovative solutions to the market, Oclaro and ClariPhy can help customers accelerate deployment of the next generation of high-speed networks."

ST's newest 3-axis accelerometer: Stingy with power, spendthrift with features

GENEVA, SWITZERLAND: STMicroelectronics has extended its motion-sensor portfolio with a 3-axis digital-output accelerometer that combines a drastically reduced power consumption – more than 90% lower than available solutions on the market - with miniature footprint and enhanced functionality.

With operating current consumption as low as 2 microamps, the 3x3x1 mm accelerometer is a perfect fit for motion-sensing features and applications in space- and power-constrained consumer devices, such as mobile phones, remotes and game controllers.

The sensor provides extremely accurate output across full-scale ranges of + or - 2g/+
or - 4g/+ or - 8g/+ or - 16g, boasting excellent stability over time and temperature.
The LIS3DH accelerometer contains a temperature sensor and three analog-to-digital converter channels for easy integration with companion chips, such as gyroscopes.

It embeds a host of enhanced features, including click and double-click recognition, 4D/6D orientation detection, and the power-saving sleep-to-wake-up mode. In this mode, the device keeps the read chain active and wakes up when an event occurs, automatically increasing the output data rate.

Other important features include a programmable FIFO (first-in first-out) memory block and two programmable interrupt signals that enable immediate notification of motion detection, click/double-click events, and other conditions.

The latest addition in ST's MEMS portfolio, the LIS3DH has been designed and produced using the same manufacturing-process technology that ST has already successfully applied to more than 700 million motion sensors sold in the market.

The device is pin-to-pin and software-compatible with all ST accelerometers in the LIS331 family, so customers can easily 'hot swap' and protect their investment in application development.

Volume production is scheduled for early Q3 2010 and the unit price is $0.85 in quantities of 100,000 units.

ClariPhy announces $24 million investment, new strategic alliances

IRVINE, USA: ClariPhy Communications, a leader in ultra high speed mixed signal, digital signal processing (MXSP) integrated circuits for optical networks, has secured $24M in series C funding.

The financing includes new strategic investors -- Oclaro, Inc., a tier-one provider of optical communications and laser components, and multiple telecom OEMs. All ClariPhy's existing venture investors participated in this round, including Norwest Venture Partners, Allegis Capital, ONSET Ventures, and Pacific General Partners.

ClariPhy will use the funding to deliver a new class of single chip MXSP ICs that significantly increase an optical network's reach and tolerance to impairments (such as chromatic dispersion, polarization mode dispersion and fiber nonlinearity), while reducing cost of ownership for both OEMs and Service Providers.

The company's line of 10G, 40G and 100G networking chips are based on advanced MXSP schemes such as Maximum Likelihood Sequence Estimation (MLSE) and Coherent Detection that approach the limits of achievable performance.

ClariPhy's implementation of these schemes in 40 nm single-chip CMOS enables equipment designers to reduce cost and power by integrating multiple system functions into customized System on Chip (SoC) solutions.

Driving demand for these MXSP ICs is the growing adoption of a variety of new broadband services from video and social networking to voice-over-IP and cloud computing. With analysts predicting that network traffic will grow by more than 40% annually over the next five years, network operators are rapidly migrating from 10G to 40G transmission rates and beyond.

"We are honored to have such a quality group of investors participate in our financing," said Dr. Paul Voois, cofounder and CEO of ClariPhy. "As transmission rates increase, network equipment designers need low-cost, low-power solutions that extend reach and minimize signal impairment across high performance networks. This funding will enable us to deliver the MXSP technology that addresses their needs. Our new partnerships with Oclaro and others open up exciting opportunities to gain insight into customer problems, integrate our innovative technology into new ASIC and SoC applications, and generate significant new revenue streams."

Owens Design receives pre-heating and cooling module follow-on orders

FREMONT, USA: Owens Design Inc., a leading design and manufacturing service provider to the semiconductor, data storage and solar capital equipment markets, announced that it has received additional follow-on orders for its turnkey wafer pre-heating and cooling module from a leading Silicon Valley semiconductor OEM.

The Owens Design BOLTS-compatible module preheats the wafer prior to placement inside the customer's process chamber, thereby improving system throughput through the reduction of process chamber heating overhead. The module also has the ability to cool post-processed hot wafers prior to cassette placement. The resulting overall throughput increase leads to a direct reduction of overall tool cost of ownership.

"Tool cost of ownership (CoO) is a significant factor in semiconductor capital equipment purchasing decisions and process throughput is a key CoO metric. Pre-heating the wafer outside the process chamber gives the customer a significant boost in process throughput, thereby helping making the customer's technology more competitive," said Bob Fung, Engineering Director for Owens Design.

"The Owens Design wafer heating and cooling module is designed to be a cost-effective, easily integrated wafer pre-heating solution that directly helps the customer achieve CoO goals and help reduce time to market."

The Owens Design's pre-heating and cooling module uses resistive heating elements that achieve better than 2 degrees Celsius uniformity wafer-to-wafer and is capable of heating a wafer up to 450 degrees Celsius in less than 15 seconds. A modular unit, the module can be integrated either standalone, or via a BOLTS compatible interface using either Ethernet or serial connections.

Custom hardware interfaces and communication protocol are also available. A water-cooled paten can be integrated into the module without changing its footprint, and process gases can be introduced into both the hot and cold processes as an extra option.

The module minimizes particulate contamination (< 1@ 0.1 micronm, PWP front side and < 1,400 @ 0.2 micronm, PWP backside). The module is highly reliable (MTBF > 20,000 hours, MTTR < 2 hours). Other than periodic cleaning, the module requires no regular maintenance.

"Contamination has become a much more critical issue with the introduction of 300 mm polished substrates," said Ernie Evans, Owens Design's Program Manager. "Developing a cost-effective pre-heating and cooling module that minimizes wafer contamination can be a very challenging process. Integrating our turnkey module into a process tool enables our customers to focus on their core technologies, reduce development costs and speed their time to market."