SAN JOSE, USA: Atrenta Inc. announced that they will conduct live demonstrations of a working 3D design flow at the upcoming Design Automation Conference in Anaheim, California on June 14-16, 2010. The live demonstrations will be conducted in the Atrenta booth (#744) and the AutoESL booth (#1577).
3D stacked die manufacturing technology holds the promise of integrating different semiconductor technologies into one high performance package, allowing the design of highly optimized systems at reduced cost and improved performance.
In order to realize the benefits of this emerging technology, design methodology and the associated electronic design automation (EDA) tools will need to be enhanced and extended to address the unique challenges associated with multi-technology system design.
The design flow that will be demonstrated at DAC is an early version of a working system that addresses 3D-aware high-level synthesis, early partitioning, floorplanning and multi-domain analysis. The system is the result of on-going collaboration between Atrenta, AutoESL and Qualcomm.
“Early partitioning, floorplanning and analysis yields substantial benefits for design predictability on conventional advanced SoCs,” said Ravi Varadarajan, Atrenta Fellow. “With the emergence of 3D multi-technology design, this activity now becomes an absolute must-have. You simply cannot hand off a 3D design to back-end implementation without knowing for certain that it is partitioned correctly.”
“High-level synthesis is finally moving into the mainstream, and complexity is driving this change,” said Atul Sharan, president and CEO of AutoESL. “The daunting challenges of 3D design demand a 3D-aware high-level synthesis approach.”
“Qualcomm has been developing a vision for a design system to address the needs of 3D for several years,” said Riko Radojcic, director of engineering for Qualcomm CDMA Technologies. “We are delighted to see our vision, PathFinding, moving closer to reality through this collaboration.”
Wednesday, May 26, 2010
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