Mentor Graphics Calibre co-development of TSMC’s iLVS simplifies modeling of advanced devices for physical verification

WILSONVILLE, USA: Mentor Graphics Corp. announced that the Calibre nmLVS product now provides comprehensive support for the iLVS interoperable rule specification used by TSMC for new design kits.

This allows customers to define and customize complex IC design rules, as needed, while maintaining compliance with TSMC specifications and allowing seamless adoption of EDA vendor performance optimizations.

The iLVS specification, which was co-developed by Mentor and TSMC, separates the rule definition syntax from underlying rule implementations. This allows Mentor to optimize the underlying implementation, reducing the need for users to tune the general rule specifications themselves.

Moreover, by using iLVS in conjunction with the Calibre nmLVS Advanced Device Properties (ADP) facility, the Calibre tool users can also establish modules for device building, enabling device model reuse and simplifying model customization for unique parameters. Previously, such customizations required manipulation of detailed SVRF scripts.

The iLVS syntax is one of two definitions jointly developed by TSMC and Mentor Graphics: iDRC, and iLVS—for describing physical verification and layout vs. schematic (LVS) rules. In addition, Mentor is also supporting TSMC’s iRCX syntax so mutual customers have a complete set of interoperable verification solutions from Mentor.

The definitions make it possible for TSMC and its customers to create verification decks that will work with the Mentor Calibre tool offerings as well as other verification products that support the specification. They also make it possible for Mentor to independently optimize the implementations to maintain performance to end users as the underlying process rules are updated by TSMC.

“The iDRC, iLVS and iRCX languages benefit both TSMC and its customers by making it possible to define and customize complex verification rules for each of our processes that can, in turn, drive verification tools from any supporting vendor,” said Tom Quan, director of EDA Alliances marketing at TSMC.

“This enables us and our customers to easily adapt design rules to new requirements or special situations without worrying about tuning and testing for different tool flows. We’ve worked closely with Mentor to co-define the architecture and syntax of these specifications and have completed validation on the Calibre tool suite as our lead implementation platform.”

“Our collaboration with TSMC on the definition of iDRC and iLVS, along with support of iRCX, makes it easier for our mutual customers to implement their own IP in TSMC decks and still maintain high performance and compliance with TSMC specifications,” said Michael Buehler-Garcia, director of Calibre Design Solutions Marketing at Mentor Graphics.

“With this collaboration, TSMC ensures their design guidelines are delivered in a consistent manner to all qualified vendors, and Mentor can use its proprietary technology to continue delivering industry leading verification platforms with the fastest and most efficient underlying code possible.”

The iDRC, iLVS and iRCX specifications are based on the open source TCL language extended with specialized functions for verification. They have been validated on the Calibre platform for 65nm and 40nm designs manufactured at TSMC, and will be rolled out as part of the TSMC reference flow for 28nm designs.

The Calibre implementation converts iDRC, iLVS and iRCX decks into highly-tuned native Calibre SVRF calls for optimum runtime performance. It also includes an interactive TCL debugger with breakpoints and variable monitors integrated with a layout debugger, which is part of the Calibre Results Viewing Environment (RVE), and a special in-line SVRF viewer.