ST's 32nm design platform for next-generation SoC ICs for networking apps

GENEVA, SWITZERLAND: STMicroelectronics has announced the full availability of a 32-nanometer (nm) technology platform for the design and development of leading-edge ASICs for networking applications.

Central to the new 32nm SoC design platform, which implements ST’s 32LPH (Low-Power High-performance) process technology, is the industry’s first Serializer-Deserializer (SerDes) IP available in 32nm ‘bulk’ silicon.

Enabling very large ASIC designs, greater than 200mm2, ST’s new 32nm 32LPH ASIC design platform enables an unprecedented mix of high performance, high complexity, low power consumption and reduced silicon real estate per functional block.

The platform is designed to accelerate the development of next-generation networking ASICs used in high-performance applications such as enterprise switches, routers and servers as well as optical cross-connect and wireless infrastructure applications.

“With the introduction of the 32LPH platform, ST is enabling the next generation of equipment for communication infrastructure applications, which requires highly integrated ASICs that can satisfy the increasing demand in performance, while also meeting extremely challenging power consumption and silicon integration goals,” said Riccardo Ferrari, Group Vice President and General Manager of ST’s Networking and Storage Division.

“We are extremely encouraged by the strong interest that customers are demonstrating for this platform, which has already gained key design wins.”

ST’s SerDes IP, called S12, is a key piece of intellectual property that has already been successfully demonstrated in labs at selected key customers. The S12 IP is vital for the development of ASICs for networking applications and enables chip-to-chip, chip-to-module and backplane communications in networking equipment designs.

“ST is the first silicon supplier to bring a full design platform in a 32nm bulk-silicon process technology to the communication infrastructure market, including a next-generation predictive ASIC top-down design methodology, together with a full set of proven IP, such as a SerDes and embedded DRAM, successfully developed over many years by ST in previous technology nodes,” said Philippe Magarshack, Technology R&D Group Vice-President, Central CAD & Design Solutions GM, STMicroelectronics.

“ST’s Technology R&D center in Crolles, France, has been instrumental in accelerating the completion of the 32LPH platform where low-power technology meets the high-performance requirements of networking applications, while still enjoying all the cost benefits of high-volume manufacturing. In addition, we have partnered with selected EDA vendors to offer networking customers the benefits of a predictable ASIC turnaround time, including fast virtual physical prototyping, and 32nm-class timing, signal and power integrity sign-off.”

The first ASIC prototypes implemented in ST’s 32LPH process technology are expected early in 2011 with production ramp-up in the second half of 2011.

ST’s 32LPH (Low-Power High-performance) design platform for networking applications supports up to 10 metallization layers to increase routing efficiency. The platform is based on the 32nm High-K Metal Gate process developed within the framework of the ISDA alliance, but also incorporates specific IP and devices from ST, such as embedded DRAM with 10-Mbit per square millimeter density and Ternary Content Address Memory (TCAM).

A SerDes (Serializer-Deserializer) is normally integrated multiple times (often up to 200) in a single ASIC chip. It enables serial communication between:
* ICs, or ASICs, on the same electronic printed-circuit board (Chip-to-Chip);
* ASICs and the Optical Module, which links to remote equipment (Chip-To-Module);
* ASICs and Physical Interface Module (Chip-To-Module); or
* ASICs and the system backplane - the backplane is the internal physical rack inside equipment in which all the system cards are mounted.

ST’s S12 IP macro, which is based on ST’s proven SerDes architecture, can be scaled up to eight 12.5-Gbit/s transmit/receive (Tx/Rx) channels per macro. The S12 has been designed with an optimal footprint for flip-chip BGA packages, and will soon be followed by ST’s S14 IP, which can reach up to 14-Gbit/s transmission speed.