LOS GATOS, USA: Silicon Frontline Technology Inc. (SFT) announced that its 3D extraction software for post-layout verification F3D (Fast 3D) has been qualified by United Microelectronics Corp. (UMC), a leading global semiconductor foundry, as the reference field solver for parasitic extraction.
UMC verified F3D’s accuracy through extensive comparison with internal benchmarks. The reliability and repeatability of results led to UMC’s adoption of F3D to generate reference data. Silicon Frontline’s F3D provides field solver accuracy for full-chip design, enabling higher quality extraction and faster post-layout verification closure.
“We are excited to add F3D as another reference field solver at UMC. We adopted Silicon Frontline’s F3D as a 3D extractor because it provides accuracy for many styles of circuitry, including high precision analog such as ADCs,” said Stephen Fu, Director of IP Development and Design Support at UMC. “This opens the door to providing higher quality silicon to customers.”
“Having UMC, a leading and well-respected silicon foundry, select F3D for generating reference parasitic extraction data boosts customers’ confidence in our results,” added Yuri Feinberg, Silicon Frontline CEO. “As customers experience F3D’s ability to accurately match sensitive parasitics, they realize more aggressive design goals are achievable and accurate design verification is possible.”
Silicon Frontline’s post-layout verification software guarantees accuracy and high performance by using rigorous 3D technology to extract parasitics. Users have the option to specify the level of accuracy desired, net by net, at the block level or with regular expressions. By guaranteeing accuracy, Silicon Frontline is ensuring the resulting parasitics are correct within the user-specified accuracy.
In July 2009, UMC validated F3D for its nanometer design processes.