BURLINGTON, USA: Gennum's Snowbush IP group, a leader in high-speed serial interface IP (intellectual property), announced that its PHY IP (operating at 6Gb/s) and Controller IP for Serial ATA (SATA), passed the series of tests necessary to obtain SATA-IO Compliance and place these IP blocks on the SATA-IO Integrators List.
Both the SATA Host IP with PHY and SATA Device IP with PHY passed the required tests specific to the SATA-IO Interoperability Program, SATA Revision 3.0.
In addition, SandForce, using the Snowbush SATA PHY IP, certified the SF-2000 for Client and Enterprise SSD configurations and is now shipping those parts in volume production.
"Collaborating closely with Snowbush, we were able to integrate their 6Gb/s SATA PHY in to our industry leading SF-2000 SSD Processor Family and establish SATA-IO certification," said Ross Stenfort, Director of Engineering, Storage Solutions, for SandForce. "Snowbush's support has been critical for SandForce to get these products to market quickly in Enterprise, Client, and Industrial SSD applications."
The SATA-IO compliance testing process involves running over 200 tests that exercise the operation of the PHY and Controller IP operating in a system supporting the SATA protocol. The tests are intended to verify the operation of a subset of the specification ensuring compatibility for Serial ATA.
The Snowbush SATA Host and Device IP tests included the PHY Transmitter (Tx) and Tx Signal Requirements, the Receiver (Rx) and Rx Signal Requirements, and the PHY Out-Of-Band (OOB) Requirements. In addition to passing the General Test Requirements, the SATA Host and SATA Device Controller IP passed Native Command Queuing (NCQ), Asynchronous Signal Recovery, Software settings, Interface Power management and Digital Optional Features.
All tests are designed to give customers confidence that the IP maintains adherence to the SATA specification, maintains compatibility with older SATA hosts and devices, and meets the standard requirements for SATA products.
"Snowbush IP is setting a new performance standard for high speed links above 5G," said Alan Tsun, GM, Snowbush. "Our SATA 6G customers can be confident we will exceed their requirements now and have the PHY technology silicon proven at 12G as the storage standards evolve further to meet the new speed requirements for SSD in SATA and SAS devices."
"SATA-IO's Interoperability Program benefits the entire industry by ensuring that high-quality, interoperable products adhering to the SATA standards are available on the market," said Mladen Luksic, SATA-IO President. "By passing these tests, the Snowbush IP demonstrates it meets the SATA Revision 3.0 requirements operating at 6Gb/s, and signals users that they can have confidence deploying Snowbush IP in high-speed SATA products."
Snowbush PHY and controller IP
The Snowbush SATA PHY exceeds the key electrical specifications for SATA applications and can be programmed to extend many operating parameters such as peak-to-peak voltage swing. A precision Clock Management Unit (CMU) includes fractional synthesis to support spread spectrum clocking and non-integer reference clock frequencies. Accessible register controls allow for user-specific optimizations for items such as driver swing, de-emphasis levels, and slew rates.
A digitally programmed receive equalizer minimizes harmful Inter Symbol Interference (ISI). All the SATA protocol low power modes are supported and the PHY is optimized for low power operation. The automatic calibration and programmability options all converge to produce a high yield, high performance SATA PHY.
The Snowbush Controller IP configures as a SATA Host or SATA Device at boot time. On the Host side an Application Host Controller Interface (AHCI) supports an interface to PCI-Express or AMBA AHB/AXI. The Device side application interface supports flow control directly to the Drive Controller.
The PHY interface complies with the SATA PHY Interface Specification (SAPIS). The SATA Controllers support ATA and ATAPI devices, Logical Bus Addressing (LBA) of 48 bits, OOB Signaling, 8b-10b Encoding-Decoding, Scrambling and Descrambling, CONT Primitive Substitution, and Elastic Buffering on the Rx path. The Host Controller also supports Scatter-gather Direct Memory Access (DMA) and First-party DMA.