Xilinx ships world’s highest capacity FPGA, shatters industry record for number of transistors by 2X

SAN JOSE, USA: Xilinx Inc. announced first shipments of its Virtex-7 2000T Field Programmable Gate Array (FPGA), the world’s highest-capacity programmable logic device built using 6.8 billion transistors, providing customers access to an unprecedented 2 million logic cells, equivalent to 20 million ASIC gates, for system integration, ASIC replacement, and ASIC prototyping and emulation.

This capacity is made possible by Xilinx’s Stacked Silicon Interconnect technology, the first application of 2.5D IC stacking that gives customers twice the capacity of competing devices and leaping ahead of what Moore’s Law could otherwise offer in a monolithic 28-nanometer (nm) FPGA. Customers are using Xilinx’s Virtex-7 2000T FPGA to replace large capacity ASICs to achieve overall comparable total costs in a third of the time, creating integrated systems that increase system bandwidth and reduce power by eliminating I/O interconnect, and accelerating the prototyping and emulation of advanced ASIC systems.

“The Virtex-7 2000T FPGA marks a major milestone in Xilinx’s history of innovation and industry collaboration,” said Victor Peng, Xilinx senior VP, Programmable Platforms Development. “Of significance to our customers is the fact that Stacked Silicon Interconnect technology offers capacities that otherwise wouldn’t be possible in an FPGA for at least another process generation. They can immediately add new functionality to existing designs while forgoing an ASIC, cost reduce a 3 or 5 FPGA solution into a single FPGA or move ahead with prototyping and building system emulators using our largest FPGAs at least a year earlier than typical for a new generation.”

Historically, the largest devices that make up an FPGA family are the last to be made available to customers. This is a result of the time it takes a new semiconductor process to ramp up and support the yields per wafer that make the largest devices economically viable. Xilinx’s Stacked Silicon Interconnect technology overcomes the challenges of yielding defect-free, large monolithic die by building the world’s largest capacity programmable logic device from four separate FPGA die interconnected upon a passive silicon interposer.

“ARM is pleased to work with Xilinx in deploying the class-leading Virtex-7 2000T device into our validation infrastructure,” said John Goodenough, VP Design Technology and Automation, ARM. “The new device underpins a flexible, yet targeted, emulation architecture and delivers a significant capacity improvement, allowing us to more easily run complete system verification and validation for our next generation processors.”

The Virtex-7 2000T device also provides equipment manufacturers with an integration platform that will help them overcome the challenges of lowering power while increasing performance and capabilities. By eliminating the I/O interfaces between different ICs on a circuit board, a system’s overall power consumption can be reduced considerably. Customers can also lower bill-of -material, test and development cycle costs when fewer IC devices are required on a circuit board. Because the die align side by side on a silicon interposer, the technology avoids the power and reliability issues that can result from stacking multiple dies on top of each other. The interposer includes over 10,000 high speed interconnects between each die enabling the high-performance integration required for a wide range of applications.

The Virtex-7 2000T FPGA gives customers the capacity, performance and power typically only found in large capacity ASICs, with the added benefits of re-programmability. For the growing number of systems and markets where economics work against ASIC development, the Virtex-7 2000T offers a unique, scalable alternative to the risk of re-spins and more than $50 million in non-reoccurring engineering (NRE) costs of a 28nm custom-made IC.

All Xilinx 28nm devices – Artix-7, Kintex-7, Virtex-7 FPGAs and Zynq-7000 EPP – share a unified architecture that supports design and IP reuse within and across families. They are all built on TSMC’s 28nm HPL (low power with HKMG) process to deliver FPGAs that consume 50 percent less static power than competing devices. Since lower static power becomes increasingly important as device capacity goes up, 28nm HPL is a key factor behind the Virtex-7 2000T device’s lower power consumption compared to designs implemented in multiple FPGAs.