SHANGHAI, CHINA: ACM Research Shanghai Ltd has introduced its newest semiconductor manufacturing platform, the integrated Ultra iSFP. The tool performs damage-free 65nm to 45nm copper (Cu) interconnect stress free polishing (SFP).
It integrates the electrochemical mechanism of SFP with ultra low down force chemical mechanical planarization (ULCMP) and thermal flow etch (TFE) to take advantage of the specific benefits of each process step, while ensuring there is no damage to the underlying device structure.
Using the Ultra iSFP to form SiO2 based air gap interconnect structures offers several advantages. Its process is simple, allowing for the use of a traditional SiO2 dielectric and damascene process, which means that no new material development is required and it eliminates damage for ultra narrow Cu line and ultra tiny interconnect structures. The tool features an automatic alignment structure, with no hard mask required. Finally, by selectively forming air gap interconnect structures in narrow line spaces, as opposed to wide line spaces, it provides both excellent thermal property for heat dissipation and excellent mechanical strength to resist pressure in packing.
“The benefits of Ultra iSFP are significant,” said David Wang, founder and CEO, ACM Research. “By capitalizing on the unique benefits of SFP, ULCMP and TFE in a single process tool, we have been able to successfully manufacture air gap interconnect structures with copper line-widths of less than 0.2 um while solving critical Cu/air-gap integration issues.”
The Ultra iSFP operates by passing the wafer through a low down force chemical mechanical planarization (CMP) process that uses endpoint detection to ensure a continuous 150nm Cu film, therefore protecting the underlying low-k structure. The wafer then undergoes a brush clean to remove large particles and a space alternating phase shift (SAPS) megasonic clean to remove tiny particles and oxide.
Following an in-tool, non-contact Cu thickness measurement, the wafer moves into the SFP process chamber to selectively remove the non-recess Cu to the barrier, followed by a bevel cleaning step. The clean wafer enters the TFE process where the barrier is removed after pre-heat, then the wafer is cooled before being transferred into the equipment front end module (EFEM) to be returned to the front opening unified pod (FOUP).
The electrochemical SFP polishing mechanism is a customer-proven critical enabling technology that ensures accurate polishing performance with no damage to the low-k and ultra low-k dielectrics. Based on a smart polishing control system, SFP is able to control global Cu line recess and dishing by using a pre-measured Cu film thickness map. Additionally, there is no erosion or deformation to the dielectric layer and barrier during the SFP polishing process, which can eliminate the damage of the Cu/low-k or ultra low-k dielectrics generated by the mechanical stress, effectively solving Cu/low-k and Cu/ultra low-k dielectric integration issues.
“The technology advances achieved with Ultra iSFP technology represent major breakthroughs in Cu/air-gap interconnect process integration. Due to its ability to reduce heat generation and increase heat dissipation, Ultra iSPF will become a critical technology to enable TSV applications,” added Wang.