Berkeley Design Automation launches nanometer circuit verification forum

SANTA CLARA, USA: Berkeley Design Automation Inc., provider of the world’s fastest nanometer circuit verification, announced the 2011 Nanometer Circuit Verification Forum, to be held September 22, 2011 at the Santa Clara Network Meeting Center in Silicon Valley’s TechMart.

This day-long event will feature leading-edge designers, university programs, and emerging EDA companies sharing successful approaches to verifying analog, mixed-signal, and RF circuits employed in 90nm to 28nm silicon. Free event registration is available at www.nm-forum.com.

Analog, mixed-signal, RF, and custom digital circuitry is the biggest differentiator and the most difficult design and verification challenge for nanometer ICs. Implemented in GHz nanometer CMOS, these circuits introduce a new class of verification challenges that traditional methodologies cannot adequately address. The Nanometer Circuit Verification Forum is a technical event that will highlight and address these challenges in detail.

The event will feature technical presentations from analog and RF circuit designers from the semiconductor industry, silicon IP companies, and leading international universities. Application areas will span state-of-the-art data converters, PLLs and timing circuits, high-speed I/O, wireless transceivers, and image sensors. Emerging verification technologies will include: nanometer device modeling, high-performance circuit simulation, full-spectrum device noise analysis, rapid prototyping with parasitic effects, variation-aware circuit design, circuit optimization, intensive circuit characterization, and thermal-aware circuit verification.

Hosted by Berkeley Design Automation the Nanometer Circuit Verification Forum is supported by EDA companies including Accelicon Technologies, Ciranova Inc., Invarian, Inc., MunEDA, and Solido Design Automation. The event will also feature a keynote by Jim Hogan, renowned veteran of the semiconductor and EDA industries.

"As we move to deeper nanometer technologies the need for combining best-in-class circuit verification solutions is greater than ever before," said Ravi Subramanian, president and CEO of Berkeley Design Automation. "The first annual Nanometer Circuit Verification Forum provides a venue for semiconductor and EDA companies to showcase innovative collaborative efforts and share the latest technology and research available to address the toughest design and verification challenges facing the semiconductor industry."