Microsemi expands SmartFusion cSoC offering for industrial and military apps

ALISO VIEJO, USA: Microsemi Corp., a leading provider of semiconductor solutions differentiated by power, security, reliability and performance, announced its award-winning SmartFusion customizable system-on-chip (cSoC) family is now available in a leaded 208-PQFP package.

The new leaded package reduces overall printed circuit board (PCB) manufacturing and debugging costs, as it requires fewer PCB layers compared to ball grid array and chip scale packages. The PQ208 is designed for a variety of industrial and military applications, including motor and motion control, gaming machines, solar inverters, military avionics, missiles and weapons.

"Launching the SmartFusion cSoC in 2010 has expanded our customer base, and a percentage of our new customers expressed the need for the PQ208 package," said Rich Kapusta, VP terrestrial products, SoC Products Group at Microsemi. "We will continue to listen to our customers and provide a robust range of solutions to suit their exact needs—from leading edge, chip scale packaging to traditional leaded packages."

As the newest option in Microsemi's cSoC portfolio, the PQ208 features an ARM Cortex-M3 based 32-bit microcontroller with up to 512KB of flash memory, up to 500K gates of field programmable gate array (FPGA) and programmable analog. It also boasts 10/100 Ethernet; external memory controller with I2C, SPI and UART interfaces; up to 113 user input/outputs (I/Os) including FPGA; microcontroller GPIO and analog I/O.

Microsemi's SmartFusion cSoCs are the only devices that integrate an FPGA, a complete microcontroller built around a hard ARM Cortex-M3 processor and programmable analog, enabling full customization, IP protection and ease-of-use. Based on Microsemi's proprietary flash process, SmartFusion devices are ideal for hardware and embedded designers who need a highly integrated SoC that provides more flexibility than traditional fixed-function microcontrollers, and significantly reduces the cost of soft processor cores on traditional FPGAs.