GLOBALFOUNDRIES announces design enablement support for 20nm design flows from leading EDA vendors

MILPITAS, USA: GLOBALFOUNDRIES announced a significant milestone on the path to market readiness of its leading-edge 20 nanometer (nm) manufacturing process. By successfully taping out a test chip using flows from leading EDA vendors Cadence Design Systems, Magma Design Automation, Mentor Graphics Corp., and Synopsys Inc., GLOBALFOUNDRIES has demonstrated that it is ready for customers to begin evaluating their 20nm designs.

“We are committed to providing customers as much of a time-to-market advantage as possible with each new technology we introduce,” said Mojy Chian, senior VP of design enablement at GLOBALFOUNDRIES. “Our model of early collaboration with EDA partners accelerates the overall development cycle, and gives customers accessibility to the inner workings of the process so they can begin targeting their designs to the most advanced manufacturing capabilities with confidence. This success is a major achievement toward market readiness of our newest process, and we will continue to enhance the design enablement support available for it.”

All four EDA companies have demonstrated that their place-and-route (P&R) tools and tech files are capable of supporting the advanced rules associated with the 20nm process. The flows include library preparation steps for double patterning technology, a complex lithography approach that raises new challenges for designers at 20nm and beyond. The 20nm test chip requires double patterning and was implemented with each EDA partner contributing a large placed and routed design. Prior to tape out, each design was thoroughly validated by GLOBALFOUNDRIES and checked against 20nm sign-off verification decks. Early and extensive 20nm collaboration with each EDA partner resulted in all designs being closed rapidly for a successful tapeout.

In addition to demonstrating full support for all of the key steps in a 20nm P&R flow—including double patterning library preparation, placement, clock tree synthesis, hold fixing, routing and post route optimization—GLOBALFOUNDRIES worked with each of the EDA suppliers to include the necessary setup and support for technology and mapping files. The flow will also demonstrate foundry support for extraction, static timing analysis and physical verification. GLOBALFOUNDRIES will make the design, libraries, and complete vendor flow scripts available to customers who wish to evaluate 20nm technology.

“The EDA360 vision calls for collaboration amongst ecosystem players to solve growing design complexity challenges. The 20 nanometer process adds several advanced manufacturing rules and requires us to collaborate with foundry partners even earlier in the development cycle,” said Chi-Ping Hsu, senior VP, Research and Development, Silicon Realization Group at Cadence Design Systems. “We will continue to work closely with GLOBALFOUNDRIES to enable our customers to predictably develop leading-edge products at advanced nodes.”

“Having achieved silicon success at the 28-nm node, several of Magma’s and GLOBALFOUNDRIES’ mutual customers are now moving to the 20-nm node,” said Premal Buch, GM of Magma's Design Implementation Business Unit. “The integrated double-pattern-compliant routing technology of Talus and mask decomposition technology of Quartz DRC combined with advanced process technology, provide Magma’s and GLOBALFOUNDRIES’ leading-edge customers with a silicon-proven design and manufacturing solution for the 20-nm node and beyond.”

“Mentor is putting in place a complete design and test flow that leverages 20nm processes, opening a wealth of options and capabilities to designers,” said Joseph Sawicki, VP, Design to Silicon Division, Mentor Graphics. “By partnering closely with GLOBALFOUNDRIES and integrating the GLOBALFOUNDRIES signoff Mentor Calibre platform with the Olympus-SoC Place and Route offering, we can provide designers with the necessary design and layout options and implementation trade-offs they require to best optimize their 20nm design requirements. Moreover, once the designs move into production, GLOBALFOUNDRIES’ use of Mentor Tessent test capabilities, interfaced with the Calibre DFM offering, enables them to accelerate the reduction in systematic yield loss.”

“GLOBALFOUNDRIES is collaborating with Synopsys to develop a comprehensive IC design flow for the 20nm process, based on the Synopsys Galaxy Implementation Platform,” said Bijan Kiani, VP of product marketing at Synopsys. “This flow makes use of some of Synopsys' most advanced tools and technologies, including the recently announced IC Compiler-Advanced Geometry place-and-route solution with full support for double patterning, In-Design physical verification with IC Validator, and StarRC parasitic extraction. The Synopsys Galaxy design flow was used successfully by GLOBALFOUNDRIES to tape out their 20nm test chip.”