Si2 announces donation of DRC+ from GLOBALFOUNDRIES

AUSTIN, USA: At the 16th Si2 Conference in Santa Clara, CA, the Silicon Integration Initiative (Si2) announced the donation of GLOBALFOUNDRIES’ DRC+ technology to Si2’s Design For Manufacturability Coalition (DFMC). The technology will be incorporated into Si2’s OpenDFM standard, which describes a high level, EDA tool independent meta-language to check for a variety of Design for Manufacturability (DFM) problems.

An industry first, DRC+ is GLOBALFOUNDRIES' silicon-validated solution to help customers accelerate time-to-volume for complex SoC designs at 28nm and beyond. The technique goes beyond standard Design Rule Checking (DRC) and uses two-dimensional shape-based pattern-matching to enable a thousand fold speed improvement in identifying complex manufacturing issues without sacrificing accuracy.

Instead of restricting the flexibility of designers, DRC+ augments standard DRC rules by applying rapid two-dimensional shape-based pattern matching to identify problematic configurations that could be difficult to manufacture. EDA tools then return specific feedback to designers on how to resolve these issues.

"GLOBALFOUNDRIES is a strong supporter of Si2’s DFMC program, as well as the OpenDFM technology. The addition of DRC+ capabilities into OpenDFM will result in a very robust standard to help customers accelerate time-to-volume for complex designs at 28nm and beyond," said Luigi Capodieci, R&D fellow and DFM director at GLOBALFOUNDRIES. "DRC+ is currently supported by all leading EDA vendors and it has received numerous innovation awards for extending the capabilities of DFM verification."

“We are excited to see the increasing momentum of the DFMC,” says Mark Mason, director for Design Data Integration at Texas Instruments. “TI has already taped out several circuits using OpenDFM rules and we are seeing return on our investment in the OpenDFM standard in the form of interoperability and reuse.” TI reports that they are planning to use OpenDFM’s DRC standard as the baseline for several of their production flows. “We are currently moving our entire 28 nm Wireless platform DRC infrastructure to the OpenDFM standard, and plan to use it at 20 nm as well,” Mason said. “OpenDFM is already paying off for TI and the addition of DRC+ capabilities is very exciting.”

“Physical verification complexity becomes multifaceted with the move to advanced process nodes. Both the EDA industry and its customers must understand and respond to these challenges,” says Pankaj Mayor, chief of Staff to CEO and acting head of Marketing, at Cadence Design Systems. “Cadence implemented OpenDFM rules on its Physical Verification System, a key Silicon Realization technology and is a co-inventor of DRC+. We believe the addition of the silicon-proven and well-accepted DRC+ technology will make OpenDFM even stronger.”