Renesas cuts design time by half on large-scale consumer SoC by using Cadence Encounter

SAN JOSE, USA: Cadence Design Systems Inc. said that Renesas Technology Corp. used the Cadence Encounter Digital Implementation (EDI) System and Encounter Conformal Low Power to layout a large-scale consumer system on chip (SoC) of over 8 million instances in one-half the time previously possible.

Cadence Encounter technology contributed significant improvements in design time and time to market for Renesas.

Time to market is critical for the highly competitive digital consumer market, and Renesas’ large-scale design (over 8 million instances) had complex power domains and a tight schedule to meet.

Given these challenges, Renesas chose Cadence solutions to overcome these critical issues and develop the SoC. Using Encounter technology for end-to-end digital design, implementation and verification, the Renesas team significantly reduced overall design time over previous design flows, and met all specifications. Renesas engineers noted EDI System’s ease of use and quick performance in designing their chip’s complex IP blocks, minimizing changes to I/O specifications and preserving the logical hierarchy of the design.

“This technology greatly helped our engineers meet aggressive schedules while providing ease of use. We are now considering deploying EDI System to other applications,” said Hideo Kameda, general manager of System Solution Business Unit 4, System Solution Business Group at Renesas Technology Corp.

Renesas was able to optimize this multi-supply, multi-voltage (MSMV) design for power leveraging the Cadence Low-Power Solution, including the Si2 Common Power Format (CPF), EDI System for implementation and Encounter Conformal Low Power for checking.

“Using the Cadence EDI System effectively, we were able to shorten our design cycle time by half against the estimated design time on our complex, 8-million-instance MSMV hierarchical design, compared to our previous design methodology. We are convinced that the EDI System is the most efficient place-and-route product for very large-scale design SoC at Renesas,” said Atsushi Hasegawa, deputy executive general manager, Design & Development Unit at Renesas Technology Corp.

“The complexities and competitive challenges of large-scale chip design require an integrated solution,” said Dr. Chi-Ping Hsu, senior vice president of implementation research and development group at Cadence. “The Cadence integrated Encounter digital design and implementation flow closes the productivity gap. We are excited to see leading semiconductor companies like Renesas select EDI System and the Cadence Low-Power Solution to achieve faster design closure and faster time to market.”