Rohde&Schwarz achieves higher quality RFICs with Cadence Virtuoso APS

FELDKIRCHEN, GERMANY: Cadence Design Systems Inc. announced that Rohde & Schwarz, a market leader in complex RF test and measurement products, improved the quality and functionality of its complex RF integrated circuits (RFICs) through an increased simulation depth using Cadence Virtuoso Accelerated Parallel Simulator (APS).

Rohde & Schwarz seeks to maximize simulation efficiency when developing key ASIC components to stay ahead of the competition and protect its IP. The Cadence simulator’s accuracy, performance and ease of use enabled the company to experience a significant simulation gain with mixed-signal RF circuits featuring as many as 64,000 mutual inductors and 3,000 actual inductors.

“The Virtuoso Accelerated Parallel Simulator increased the productivity in our analog verification efforts, enabling exhaustive simulation and reducing the risk of errors,” said Gerhard Kahmen, head of R&D Mixed-Signal IC at Rohde & Schwarz. ”We were very pleased to increase overall simulation depth across various classes of circuits by factors of 4 to 16.”

“Conventional simulators are not able to simulate and verify ICs with such a complexity and accuracy,” said Zhihong Lui, corporate vice president at Cadence.

“With the Virtuoso Accelerated Parallel Simulator, Rohde & Schwarz is now in the position to create RF simulation plans that are substantially more comprehensive than before. Our simulator helps our customers to simulate not just parts of the circuits but to simulate RF subsystems with large numbers of mutual and actual inductors, regardless of the process nodes used.”

The Virtuoso Accelerated Parallel Simulator delivers the full accuracy of the Virtuoso Spectre Circuit Simulator, used by Rohde & Schwarz as their sign-off simulator.

Developed to solve the largest and most complex analog and mixed-signal designs across all process nodes, the APS simulator consists of a combination of proven Cadence simulation technologies and a breakthrough parallel circuit solver, along with a newly architected engine that efficiently harnesses the power of multiprocessing computing platforms.