MIPS Technologies, Virage Logic to offer optimized embedded memory IP

SUNNYVALE & FREMONT, USA: MIPS Technologies, a leading provider of industry-standard processor architectures and cores for digital consumer, home networking, wireless, communications and business applications, and Virage Logic Corp., the semiconductor industry's trusted IP partner, are teaming to offer optimized embedded memory IP for joint customers.

With SRAM memory instances from the Virage Logic ASAP 90nm and SiWare 65GP High Density SRAM compiler families specifically optimized for MIPS32 processors, customers can speed development of complex SoCs targeted for Blu-ray DVD, HDTV, IPTV, set-top box and broadband customer premises equipment (CPE) devices.

"To support the rapidly growing consumer multimedia market, we're working with companies in the MIPS ecosystem to provide integrated solutions that help customers get to market quickly with greatly reduced system costs," said Art Swift, vice president of marketing, MIPS Technologies. "As a part of this strategy, we are pleased to team with our long-time physical IP partner Virage Logic to offer optimized memories that help customers reach performance levels simply not possible from other embedded CPU vendors at these price points."

"Virage Logic is excited to work with MIPS Technologies on yet another collaborative effort to benefit set-top box and broadband developers," said Brani Buric, executive vice president of marketing and sales at Virage Logic. "By integrating high speed instances from Virage Logic's SiWare and ASAP memories with MIPS processors, our customers can achieve a tightly-integrated, high-performance solution that accelerates chip development, helps manage cost, and shortens time-to-market."

The ASAP 90nm and SiWare 65GP SRAM instances were jointly developed by MIPS Technologies and Virage Logic for the MIPS32 4KE, 24K, 24KE, 34K, 74K and 1004K processor core families.

Each Virage Logic ASAP and SiWare Memory High Density SRAM instance is offered at a special price compared to a full-featured SRAM compiler. Additional instances and full featured compilers are also available.