Avnet Spartan-6 FPGA DSP development kit jump starts DSP designs

PHOENIX, USA: The Avnet Electronics Marketing operating group of Avnet Inc. has introduced the Xilinx Spartan-6 FPGA DSP Development Kit.

Order entry is now open for the $1,995 kit, which includes a device-locked version of ISE Design Suite: System Edition 11.4. Spartan-6 FPGAs produce up to 45 GMACs of performance in a single part, offering the ideal solution for cost-prohibitive designs.

The Spartan-6 FPGA DSP Development Kit enables users to focus on the unique value of their design with an easy entry point for using FPGAs for DSP. Aerospace and defense, wireless, ISM and other computationally-intensive applications demand digital signal processing performance and cost effective solutions.

“With the introduction of the Spartan-6 FPGA DSP Kit, Avnet is offering its first DSP development platform for customers who need greater performance and low cost,” said Jim Beneke, vice president, global technical marketing at Avnet Electronics Marketing. “This kit will help our customers quickly learn the different tool flows and design techniques involved in creating DSP-centric designs with the Spartan-6 FPGA family.”

The Spartan-6 FPGA DSP Development Kit combines a scalable development board, DSP IP, DSP Development tools, and a preconfigured and fully validated Spartan-6 DSP Targeted Reference Design.

This design serves as a basis to illustrate DSP techniques and design flows for the Spartan-6 class of signal processing functions. The state of the art digital up converter (DUC)/digital down converter (DDC) Targeted Reference Design shows customers how to use advanced techniques such as clock over-sampling, time division multiplexing and signal processing and resource optimization with the high performance DSP48 slices.

Both, an RTL and model-dased design flows are included. The design flow, based on MATLAB and Simulink from the MathWorks, allows algorithm developers to create DSP hardware designs using a familiar modeling environment without the need to learn RTL. Experienced RTL designers are provided design techniques for creating efficient DSP hardware using ISE Design Suite and LogicCoreTM DSP IP along with verification methodologies for comparing functional correctness against high-level algorithm models.