OVP releases vendor-verified high performance models of Virage Logic’s ARC processors

THAME, ENGLAND: The Open Virtual Platforms (OVP) initiative has released models of Virage Logic’s ARC processor cores. Models of the Virage Logic ARC 600 and ARC 700 families of processor cores have been released, including the ARC 605.

Additionally, Virage Logic and Imperas have co-operated on the verification of the functionality of the models. Virage Logic’s ARC line of processor cores, the world’s second most widely used processor architecture, are commonly used in audio and video subsystems, and in flash controllers, among other applications.

These models work with the OVP simulator, OVPsim, where they have shown exceptionally fast performance reaching hundreds of millions of instructions per second. The models are free and available as open source from the OVP website.

All OVP processor models are instruction accurate, and very fast, focused on enabling embedded software developers, especially those building hardware-dependent software such as firmware and bare metal applications, to have a development environment available early to accelerate the software development cycle.

Virtual platforms utilizing these OVP processor models can be created with the OVP peripheral and platform models, or the processor models can be integrated into SystemC/TLM-2.0 based virtual platforms using the TLM-2.0 interface available with all OVP processor models.

“Imperas is moving the embedded systems industry forward with its visionary approach to virtual platforms and the easy accessibility of OVP,” said Dr. Yankin Tanurhan, vice president and general manager, processor and NVM solutions, for Virage Logic.

“Verifying the compatibility and functionality of these high-performance models of our ARC processors and making them freely available is a huge advantage for design teams worldwide. This availability will help enable them to develop high-quality software faster and more easily using virtual platform models of their complete SoCs and embedded systems.”

“As the semiconductor industry’s trusted IP partner, Virage Logic recognizes the importance of freely available models to enable rapid growth and accelerate the design and programming of embedded systems on chip,” said Simon Davidmann, president and CEO, Imperas and founding director of the OVP initiative.

“Compatibility and quality of models is essential when using virtual platforms to develop software. Offering free, verified processor models means developers can get higher quality software developed faster and help close the software gap.”