Virage Logic intros MIPI D-PHYs and controllers on 40LP process

FREMONT, USA: Virage Logic Corp. has announced the availability of its SiPro MIPI Rx D-PHY and MIPI Tx D-PHY as well as CSI Rx (camera serial interface receiver) and DSI Tx (display serial interface transmitter) controllers on the 40LP process node in Q2 of this year which are based on the production proven D-PHYs announced last year.

Virage Logic's production proven SiPro MIPI CSI and DSI D-PHYs and controllers are immediately available on the 65LP process node. Development costs for such complex MIPI PHY SERDES typically run higher than 40 man-years.

Virage Logic's SiPro MIPI Rx D-PHY and Tx D-PHY solutions are system-on-chip (SoC) verified and fully compliant with the latest D-PHY v1.00 MIPI standard. Shipping in a mobile device for over a year, the production proven SiPro MIPI Rx D-PHY and Tx D-PHY has been proven to consume the lowest power with minimum silicon area and significantly reduced design risk. Specially architected for a faster improvement in chip yield, the IP solution expedites volume ramp-up to ensure maximum production success.

"Compared to alternative bi-directional solutions on the market, the SiPro MIPI solution provides 70 percent area savings, 80 percent lower power consumption, approximately 20 percent better performance and high yields through yield-calibration circuitry," said Kamalesh Ruparel, vice president and general manager of Virage Logic's ASIP Solutions Group.

"With Virage Logic's industry leading production proven technology on advanced process nodes and its optimized characteristics, customers get to market faster while meeting stringent power and silicon cost budgets."

"The MIPI interface will do well," said Will Strauss, President of Tempe, AZ-market research firm Forward Concepts. "With the major semiconductor players, such as Texas Instruments on its upcoming OMAP 4 chip and ST Micro as a major Nokia chip supplier, beginning to incorporate the interface on their devices, the market should grow nicely."