Energy Micro uses Cadence low-power solution to develop energy-efficient MCU

FELDKIRCHEN, GERMANY: Cadence Design Systems Inc. announced that Energy Micro, the energy friendly microcontroller company, deployed Cadence Low-Power Solution, to develop a highly power efficient ARM Cortex M3-based microcontroller that significantly saves battery life.

“We set out to develop a product that is unique in the market, and the Cadence Low-Power Solution was an important enabler to our success. The comprehensive flow covers all stages of the design and maintains our power intent throughout,” said Geir Førre, CEO of Energy Micro.

“Our 32-bit microcontroller has the lowest active-mode energy consumption and lowest standby energy available today. When designed into low-power devices running from a 3V lithium cell, the device prolongs battery life by 4X.”

The Cadence Low-Power Solution provides a complete design-to-signoff methodology based on the CPF (Common Power Format). The flow starts with early design planning and system architecture, and continues through front-end design, functional verification, synthesis, physical implementation, packaging, and signoff. The integrated solution preserves design intent for power and provides a robust estimation and verification methodology, minimizing the risk of functional or structural flaws.

“With its low-power microcontroller unity, Energy Micro has set a milestone in the development of energy-friendly devices,” said Sandeep Mehndiratta, solutions marketing group director at Cadence. “The Cadence Low-Power Solution is at the forefront of this effort, providing an end to end methodology that enables power efficient chip design.”

The comprehensive low-power flow from Cadence supports power exploration, estimation, and analysis at every step including C-level design exploration, software optimization, RTL synthesis, and signoff. Along with the implementation flow, power verification is utilized to enable first-pass success. By leveraging static, dynamic, and formal power verification techniques in a closed-loop verification methodology, design teams can eliminate last-minute power-related surprises.