Arasan first to market with MIPI D-PHY rev 1.1 compliant PHY IP

SAN JOSE, USA: Arasan Chip Systems Inc. announced the availability of the upgraded MIPI D-PHY IP Core, the latest addition to its prominent PHY portfolio. On December 16, 2011 the MIPI Alliance board approved version 1.1 of the D-PHY specification, which defines the physical layer support of up to 1.5Gbps per data lane.

As part of Arasan's market leading practices, the company has already taped out a D-PHY 1.1 implementation in a 40nm process, with full support of 1.5 Gbps data rates on each of the four data lanes. This level of throughput allows, for example, tablet and panel designers to combine the D-PHY with Arasan's MIPI DSI cores to achieve QXGA resolutions at 60 frames/sec and QSXGA at 30 frames/sec.

Meeting D-PHY specifications at 40 nm and below often presents a challenge. At 40 nm, for example, the core supply voltage may be limited to 1.1 volts, which is the minimum allowed for the D-PHY to operation in Low Power (LP) mode. The nominal voltage required for the D-PHY to operate in LP mode is 1.2 volts, which may not be available. Arasan has responded to this challenge by providing designers three choices.

One is to provide an extra power pin for a dedicated 1.2 volt supply to be provided from an external source on the PCB. The second is to allow the native 1.1 core voltage to drive the D-PHY in LP mode which, if ensured by the designer to be the minimum available at all times, will maintain a functional link. The final option is to use an Arasan supplied LDO that steps down a 1.8/2.5/3.3V external supply to the nominal 1.2V required by the specification. This alternative comes with a small area overhead.

"Arasan continues to lead with the broadest portfolio of MIPI digital and analog IPs", said Andrew Haines, VP of Marketing at Arasan. "Our MIPI D-PHY IP is the result of the close interaction between Arasan and MIPI Alliance members to ensure rigorous compliance with the specification."

The Arasan D-PHY IP core is fully compliant to the D-PHY specification version 1.1. It supports the MIPI® Camera Serial Interface (CSI-2) and Display Serial Interface (DSI) protocols using the standard MIPI® PPI interface. It is a universal PHY that can be configured as a transmitter, receiver or transceiver with built-in test features. The D-PHY consists of an analog front end to generate and receive the electrical level signals, and a digital back end to control the I/O functions.

Arasan's MIPI D-PHY IP Core is available immediately for licensing, including GDS-II for a variety of foundry processes, Verification IP, all physical integration support files, and documentation.