Open Virtual Platforms selected by NEPHRON+ EU research project for software development environment

OXFORD, ENGLAND: NEPHRON+, an EU research project, has recently selected Open Virtual Platforms (OVP) tools for its software and test development environment. Key factors in its decision were ease of use and flexibility of OVP, as well as the availability of ARM processor models chosen for the electronics system.

The NEPHRON+ project is developing a wearable artificial kidney and personal renal care system. According to Frank Poppen of OFFIS - Institute for Information Technology of Germany, the lead institution in the consortium for the embedded software development, “OVP was selected because of the ease with which models are built and the flexibility in interfacing to other tools. The availability of the ARM processor model we needed, and the open source nature of the OVP models, were also important factors.”

One of OFFIS’s development milestones was to interface the OVP simulator, OVPsim, to the Simulink system simulator. This was done to enable testing of the target software, running directly on the processor in the virtual platform, with the full system environment. Due to the open nature of the OVP technology, OFFIS was able to write its own interface model, which is now available on the OFFIS website.

“OVP is addressing key issues in software development for embedded systems,” said Noel Hurley, VP Business Development, ARM. “By supporting the creation of virtual platforms, OVP is enabling early software development and helping expand the ARM user community.”

OVP processor models are instruction accurate, and very fast. They enable the early creation of software development environments for embedded software developers looking to create hardware-dependent software such as firmware and bare metal applications. OVP processor models employ a state of the art just-in-time code morphing engine to accelerate simulation speeds. Virtual platforms utilizing these OVP processor models can be created with the OVP peripheral and platform models.

The processor models can also be integrated into SystemC/TLM2 based virtual platforms using the native TLM2 interface available with all OVP models. The native TLM2 interface enables multiple instantiations of the processor models in a single virtual platform, just as any other component would be instantiated. The OVP simulator can also be encapsulated within the Eclipse IDE, enabling easy use for software developers.

The OVP library of Fast Processor Models includes the complete families of the ARMv4, ARMv5, and ARMv6 architecture-based processors, as well as models of most of the processors in the ARM Cortex-M series and Cortex-A series processors. In addition to working with the OVP simulator, these models work with the Imperas multiprocessor/multicore software development kit, M*SDK, which includes advanced tools for multicore software verification, analysis and debug, including key tools for software development on virtual platforms such as OS and CPU-aware tracing, profiling and code analysis.

“ARM users recognize the importance of virtual platforms to accelerate the development of software for embedded systems,” said Simon Davidmann, Imperas CEO, and OVP founding director. “Compatibility and quality of models is essential when using virtual platforms to develop software, and having validated processor models available for free from OVP means developers can get higher quality software developed faster. Validated models really help to close the Software Gap.”