MOUNTAIN VIEW, USA: Analog Bits, the Integrated Clocking and Interface IP leader, unveiled a new cable-specific SERDES IP specifically targeting the cost-sensitive, yet performance demanding consumer cable market.
The latest addition to the Analog Bits SERDES IP product line allows customers to use low cost cables with SERDES at either end to recover and retime the signal and has been demonstrated with multiple cables including FFC ribbon, Micro-Coax and Dual-Coax.
"Cable cost is a critical consideration for our consumer electronics customers," explains Mahesh Tirupattur, executive VP, Analog Bits, "Our SERDES IP offers unique low power capability that improves signal integrity with incredibly low bit-error-rate."
The pin-configurable macro uses standard CMOS logic process devices and exhibits exceptional input sensitivity, jitter tolerance and sophisticated equalization. Its low pin count, low power and compact form factor – 0.095 mm2 active silicon area per lane – make it suitable for a variety of flip-chip and wire-bond packages embedded in connectors. The serial client interfaces can connect directly to SFPs and operate
over a wide range of frequencies from 125 Mb/s up to 12.5 Gb/s.
All Analog Bits' Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports multi-protocol market needs including a wide range of AC-coupled high-speed serial communication standards requiring serial Clock Data Recovery (CDR).
Analog Bits' proprietary and industry leading PLL technology, in combination with sophisticated circuit techniques and innovative I/O design makes this macro an extremely area and power efficient solution. The PMA can be integrated with the available PCS to provide a PCI-Express Gen1/Gen2/Gen3 PHY solution, and has interface capability to allow integration with other customer-designed serial protocol PCS layers.