Wednesday, March 28, 2012

Synopsys' collaboration with industry consortium yields double patterning technology models for parasitic extraction

MOUNTAIN VIEW, USA: Synopsys Inc. announced that its collaboration with the members of the Interconnect Modeling Technical Advisory Board (IMTAB) of the IEEE Industry Standards and Technology Organization (IEEE-ISTO) has resulted in a parasitic variation modeling solution to address the effects of double patterning technology (DPT), targeted for use in 20-nanometer (nm) IC manufacturing.

The new DPT model extensions will be available to the EDA and semiconductor industries through the open source licensed Interconnect Technology Format (ITF) version 2012.06 ratified by IMTAB members, including Apache Design – a subsidiary of ANSYS, GLOBALFOUNDRIES, NVIDIA, Synopsys and others.

DPT is a critical technique for ensuring printability of device and interconnect layers in 20-nm IC manufacturing. However, splitting layers into two masks can introduce timing variations as a consequence of mask misalignment in the manufacturing process. To enable successful 20-nm design tapeouts and manufacturing, the IMTAB members determined that a DPT-aware modeling solution for parasitic extraction was needed to account for the timing impact and address it in the physical implementation and signoff design flow.

"The real challenge was developing a solution that accurately modeled the impact on timing with no productivity change to the flow," said Bari Biswas, chair of IMTAB and senior director of engineering for extraction solutions at Synopsys. "While working with IMTAB and leading foundries, Synopsys developed a novel modeling technique that eliminates the need to insert the time-consuming coloring step during the implementation and signoff flow, with negligible impact on extraction runtime."

"The manufacturing requirements at advanced process nodes, such as double-patterning lithography at 20-nanometers, are driving an industry-wide, intensive focus on newer parasitic modeling techniques to achieve signoff accuracy and performance," said Richard Trihy, director of design methodology at GLOBALFOUNDRIES. "GLOBALFOUNDRIES is pleased to be working with the industry-leading IMTAB member companies and lending our extensive knowledge of advanced processes to develop innovative solutions that address these common challenges. Our close collaboration has resulted in several enhancements to ITF modeling at the 28-nanometer node, and GLOBALFOUNDRIES is now driving silicon-validation of the latest DPT modeling at the 20-nanometer node."

In addition to DPT modeling, IMTAB has also approved enhanced trench contact device modeling extensions in the ITF to include evolving 20-nm characteristics. The trench contacts are used for local device interconnections that improve density and lower resistance. However, additional challenges are introduced in modeling co-vertical conductors and associated large fringe capacitances. To deal with these issues, specific 20-nm extensions were added to explicitly model silicon dielectric underneath the device and the special dielectric region between the gate and raised diffusion to enable accurate modeling of the new parasitic effects.

"IMTAB members continue to collaborate on challenges facing the semiconductor industry in new process nodes such as 20-nanometer," said Marco Migliaro, president and CEO at IEEE-ISTO. "To improve tool interoperability around ITF modeling, IMTAB will help the industry realize a single, proven format to help speed design flows."

The next IMTAB meeting is scheduled for Tuesday, May 22, 2012.

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