MoSys demos bandwidth engine IC interoperability with LSI SerDes

SANTA CLARA, USA: MoSys, a provider of serial chip-to-chip communications solutions that deliver unparalleled bandwidth performance for next generation networking systems and advanced system-on-chip (SoC) designs, has successfully demonstrated interoperability of its Bandwidth Engine IC with the SerDes characterization and evaluation board from LSI Corp.

MoSys’ Bandwidth Engine SerDes is compatible with the OIF CEI-11G specification, allowing it to interface with OIF compliant transceivers, such as those available from LSI. The GigaChip Interface used by the Bandwidth Engine IC is a 90 percent efficient, no-cost, open transport protocol optimized for chip to chip communications. This demonstration shows the Bandwidth Engine IC communicating with LSI 15G SerDes test vehicle silicon at 10.3125Gbps using a PRBS31 pattern.

“LSI is well-known as one of the world’s leading providers of high-performance communication processors and custom silicon solutions and is renowned for its serial high-speed interface technology. Having interoperability between our Bandwidth Engine and high performance SerDes designed by LSI is an important milestone for future opportunities,” stated David DeMaria, VP of Business Operations for MoSys.

“Next generation data center and mobile infrastructure applications require ever increasing memory content and bandwidth to keep up with end user data,” stated Harold Gomard, LSI SerDes product manager. “Interoperability between MoSys' Bandwidth Engine and LSI SerDes technology enables our customers to realize a lower risk and faster time to market solution.”