AUSTIN & ALBANY, USA: Engineers from SEMATECH’s Front End Processes (FEP) program will present technical papers revealing research breakthroughs at the 55th annual IEEE International Electron Devices Meeting (IEDM) from December 7-9, 2009, at the Hilton in Baltimore, MD.
SEMATECH experts will report on low defect density high-k gate stacks for alternative III-V channel materials and non-planar devices, and discuss a new dry etch approach to minimize etch related leakage—a significant process technology advancement for next-generation logic and memory technologies.
“SEMATECH continues to make critical contributions to materials and process technology advancements for next-generation logic and memory devices. The industry is always looking for cost-effective technical solutions that are practical for manufacturing and SEMATECH’s front-end engineers are working to find new ways to extend CMOS in existing markets and to create opportunities for new emerging applications,” said Raj Jammy, SEMATECH’s vice president of materials and emerging technologies.
“We are excited to share our research results with the technical community at the IEDM, which has always been a premier forum for sharing breakthrough developments in materials and process technologies for transistor and memory scaling.”
Additionally, SEMATECH will host an invitational pre-conference workshop entitled “Emerging Technologies in Solid State Devices” from December 5-6.
The two-day workshop will focus on technical and manufacturing challenges affecting emerging memory technologies, energy-efficient devices, and III-V channel materials in CMOS devices. Co-sponsored by Tokyo Electron Ltd and Aixtron AG, the workshop will feature experts from industry and academia debating the challenges and opportunities in these areas in a series of presentations and panel discussions.