SANTA CLARA, USA: Calypto Design Systems, the leader in sequential analysis technology, today announced that Intrinsity Inc. is deploying Calypto’s SLEC RTL tool for the comprehensive verification of its products.
Intrinsity implements industry-standard, cycle-accurate RTL cores from ARM, PowerPC and MIPS in its Fast14 one-of-N domino logic to increase performance by as much as 65 percent, while maintaining low leakage and operating power characteristics in approximately the same silicon area.
“Calypto’s SLEC RTL is critical to our design process because it is the only tool in the market that provides comprehensive verification of complex sequential optimizations,” said Mark McDermott, general manager and vice president of engineering at Intrinsity. “It is an integral part of our verification methodology.”
SLEC RTL, a sequential logic equivalence checker, enables designers to verify that the introduction of sequential optimizations such as clock gating, retiming and re-pipelining do not alter the functionality of designs. SLEC RTL also dramatically reduces the time, effort and cost associated with running extensive, resource-consuming simulation regressions.
“Innovative power and performance optimization techniques are the key differentiators for today’s processor and DSP technology providers,” said Tom Sandoval, CEO of Calypto Design Systems. “SLEC RTL provides designers at Intrinsity the confidence to use unconventional design methods to deliver substantially higher performance, lower power solutions.”