Tier Logic announces innovative 3D-FPGA technology

SANTA CLARA, USA: Tier Logic, Inc., a privately held fabless semiconductor company, has introduced its new 3D-based technology for FPGAs and ASICs, known respectively as its TierFPGA and TierASIC devices.

Tier Logic is the only company to solve the digital designer's dilemma: Should their system use an FPGA, which is ideal for making quick, easy design changes, but is expensive in terms of cost and power? Or is an ASIC a better choice?

An ASIC has cost and power benefits, but has traditionally meant high risk and high development costs. Tier Logic’s innovative 3D-FPGA technology approach offers the best of both worlds—flexibility in design AND low cost in production.

Tier Logic's 3D-FPGA technology
Tier Logic separates user circuits and configuration circuits into three-dimensional (3D) stacked layers. Reducing the configuration overhead from the base-layers of silicon allows Tier Logic to produce smaller, denser, faster, lower-power, and more reliable FPGAs.

In addition, once the design is stable, the programmable configuration circuitry layer can be replaced by a simple metal layer and turned into an ASIC version. However, unlike any other type of ASIC conversion, the timing remains identical between the FPGA and ASIC, allowing zero-risk, zero-effort conversions.

Industry-standard tool flow
Although Tier Logic’s 3D structure is different from other FPGAs, users will be very familiar with the architecture and tool flow when they design with the Mobius tools from Tier Logic because they have the same features as existing FPGA providers and the design flow is exactly the same.

New or existing FPGA designs are easily synthesized, packed, placed, and routed into Tier Logic devices using industry-standard design tools, such as Precision Synthesis from Mentor Graphics, combined with Tier Logic's Mobius design tool suite. Mobius tools also create the bitstream for TierFPGA devices and the metal-mask data for TierASIC devices.

Tier Logic CTO Raminda Madurawe commented: “The innovation of Tier Logic's monolithic 3D-FPGA significantly enhances the value of programmable solutions. By moving programmable overhead into the third dimension, we improve cost, power, performance, and security – all of the drawbacks associated with traditional FPGAs – without losing programmability. We can remove this overhead completely from the device without altering implemented designs to offer users timing-exact, very-low-cost ASICs—something traditional FPGAs simply can't offer.”

TierFPGA devices
Like other mainstream FPGAs, TierFPGA devices use SRAM cells to store programming information. However, in the Tier Logic 3D-FPGA structure, these SRAM cells are implemented monolithically in an additional silicon layer built from thin-film transistors (TFTs) that sits on top of the user’s active logic. By pulling these cells out of the active logic layer, the chip area is reduced and the active logic blocks are moved closer together. This smaller, stacked FPGA structure results in lower cost, lower power, and higher performance.

Tier Logic products are fabricated using the company's patented process technology. All devices in the product family are offered in FPGA and ASIC platforms. Tier Logic utilizes two interchangeable process techniques to fabricate configuration circuits. The FPGA family uses reprogrammable TFT SRAM for configuration, while the ASIC family uses a one-mask hard-wired customer bit pattern for configuration. Thus, all features and resources found in the FPGA are also identically duplicated in the equivalent ASIC. This process allows a single design, once finalized, to be fabricated either as an FPGA or as a timing-exact ASIC with zero risk and with no additional engineering effort, time, or cost.

TierASIC devices
The structure of the TierFPGA device was designed to transition effortlessly from a prototype FPGA platform to a low-cost ASIC platform. Once the TierFPGA design is frozen and signed off, the bit-stream information is used to create a single custom-mask metal layer that will replace the SRAM programming layer, resulting in a cost-reduced TierASIC device for high-volume production.