CUPERTINO, USA: Parallel Engines Corporation today announced its intention to deliver a toolset for merging Semiconductor-IP (IP) and Electronic Design Automation (EDA) into one system.
The Company plans to deliver tools with bundled models for a new class of engineering desktop applications. By bundling IP information, libraries, physical models and tools IP evaluation and integration can be done up front without back-end team tools and the nuisance of collecting massive amounts of EDA data.
Parallel Engines is the brainchild of George Janac, founder of Chip Estimate; High Level Design Systems, and startup investor. While the company seems to be focused on a new generation of Floorplanning it is really focused on making physical IP integration. Tools must have functional knowledge to deal with today’s reality and 20-plus vendors contributing to a single design. The Company sees access to information as the key to dramatically reducing costs of large complex SoC, mobile and networking chips.
Parallel Engines is staffed by veterans who realize that now is the time to move beyond the current EDA boundaries. EDA is slow to embrace web-connectivity. But this is the way of the world and the only way to interact with a supply chain. Parallel Engines will launch a series of web sites to help designers get access to information in a centralized fashion. Conversely its IP-Integration desktop will reach out and gather supply chain data.
“Today we have ‘Smart’ everything, phones, power, pars,” said founder George Janac, “but where is smart EDA, smart IP? Tools would not recognize a 10 gigahertz SerDes from a Real time clock. EDA has to become application smart.” The only way for design costs to be dramatically reduced is for EDA to integrate IP and IP Vendors to ship blocks with EDA tools.
The Company plans to announce, and release, its initial products over the next two months.