nSys demos verification IP for PCIe 3.0

NEWARK, USA: nSys Design Systems will demonstrate their Verification IP for PCIe 3.0, which is currently at preliminary revision 0.5, at the PCI-SIG DevCon 2009.

“In our endeavor to take PCI to the next generation, we have consistently relied upon PCI-SIG member companies including nSys as part of the PCIe ecosystem,” said Al Yanes, chairman and president, PCI-SIG.

“nSys has been actively sponsoring the PCI-SIG developers conferences around the world for more than five years now and we appreciate their willingness to share their experiences and expertise by presenting papers that benefit other members.”

“nSys has a comprehensive Verification IP for PCIe 2.0/ 1.0, in native Verilog and System Verilog,” said Atul Bhatia, CEO, nSys Design Systems.

“As PCIe is still evolving, it is our endeavor as an observer of the protocol working group, to make available the interim solutions for Verification IP to industry leaders.”