MOUNTAIN VIEW, USA: Synopsys Inc. announced that Teradici Corp., a provider of groundbreaking PC-over-IP technology, has signed an expanded business agreement to establish Synopsys as its primary EDA partner.
As a result of the latest multi-year agreement, Teradici has consolidated on Synopsys' Galaxy Implementation and Discovery Verification Platforms for its implementation, verification and analog/mixed-signal flows, as well as extended their use of Synopsys DesignWare IP cores and consulting services.
"Over the past several years, we have built a successful relationship with Synopsys by utilizing their best-in-class design tools, interface IP and design services to mitigate our project risks and accelerate the delivery of our breakthrough technology to our customers," said Maher Fahmi, vice president of Silicon Engineering and co-founder, Teradici.
"As we grow our competencies in new areas such as analog design and simulation, we know we can continue to rely on the breadth and quality of Synopsys' technology and the outstanding support of its field and services teams."
"In today's challenging business climate, innovative chip developers like Teradici are looking for partners who will not only help them distinguish their products, but do so in a manner that makes them more efficient and productive across all their design flows," said John Chilton, senior vice president of marketing and strategic development at Synopsys.
"Our broadened relationship enables Teradici to take advantage of Synopsys' growing technology and services portfolio so they can focus on developing and delivering their unique network-delivered computing products to the marketplace."
As part of the new agreement, Teradici has expanded access to products, services and IP from Synopsys, including the Galaxy Implementation Platform's IC Compiler place-and-route technology, Design Compiler Ultra synthesis, Galaxy Custom Designer mixed-signal implementation, DFTMAX compression, TetraMAX automatic test pattern generation, PrimeTime SI signal integrity analysis, Star-RCXT parasitic extraction and Hercules physical verification; the Discovery Verification Platform's VCS, HSPICE, and HSIM simulators for analog and digital verification, and MVRC and MVSIM for low power verification; and DesignWare IP for USB 2.0 and Ethernet.