Xilinx Virtex-6 FPGAs enable highest PCIe bandwidth

BANGALORE, INDIA: Xilinx today announced that its newest generation Virtex-6 FPGA family is compliant with the PCI Express 2.0 specification, delivering up to 50 percent lower power than previous generations and 15 percent higher performance than competitive offerings.

The second-generation PCIe block integrated in Xilinx Virtex-6 FPGAs has passed PCI-SIG PCI Express version 2.0 compliance and interoperability testing for 1 to 8-lane configurations, adding to the broad range of design resources from Xilinx and its alliance members that support the widely adopted serial interconnect standard.

This significant industry milestone is expected to accelerate mainstream development of high bandwidth PCIe 2.0 systems for communications, multimedia, server and mobile platforms, enabling applications such as high definition video, high-end medical imaging, and industrial instrumentation among others.

In addition, Xilinx has once again teamed up with key alliance members Northwest Logic Inc. and PLDA to provide Direct Memory Access (DMA) intellectual property (IP) cores for Virtex-6 FPGAs.

This latest collaboration builds on their existing PCIe 2.0 soft IP for Virtex-5 FXT devices, the first FPGA to provide PCIe 2.0 x8-lane support with the Northwest Logic DMA core. DMA engines enable the efficient movement of data in systems, ensuring that the PCIe block in Virtex-6 FPGAs delivers maximum performance and bandwidth.

“With increasing adoption of PCIe Gen 2 for meeting high bandwidth connectivity requirements, many of the VLSI/System design houses in India are increasingly engaging global customers in use of this protocol as part of their overall system designs,” said Neeraj Varma, Country Manager - Sales, for India and Australia and New Zealand at Xilinx.

“By offering this as Hard IP in Virtex-6 along with reference designs, the design houses in India can offer a very compelling solution to their end customers -- by reducing the overall project timeline along with the total cost of ownership."

Designers can immediately begin the evaluation and design of PCI Express 2.0 compliant systems in Virtex-6 FPGAs. To assist in this effort, the Xilinx CORE Generator system delivered in the ISE Design Suite provides the PCIe core, reference design and all the scripts, basic testbench, and simulation models needed to streamline integration into customer designs.

Designers can download at no charge the ISE WebPACK software or trial version of the full featured ISE Design Suite from Xilinx web site at: www.xilinx.com/tools/webpack.

“The demand for high-bandwidth connectivity is insatiable, and the PCIe 2.0 standard is critical to meeting the requirements of high performance, low power applications, especially in the telecommunications and server markets,” said Tom Feist, senior marketing director for ISE Design Suite at Xilinx.

“Integrated PCIe FPGA blocks eliminate the I/O bottleneck in maximizing system performance, and were first introduced with our Virtex-5 FPGAs. Now with Virtex-6 FPGAs, designers in the pursuit of even higher bandwidth can take full advantage of our production-proven PCIe implementation with up to 50 percent lower power than the nearest competitive offering.”

Production-proven PCIe support
Xilinx continues to lead the FPGA industry in support for PCI Express solutions. Xilinx was the first to integrate compliant PCIe version 1.1 blocks into programmable devices with its Virtex-5 FPGA family.

PCIe 2.0 soft IP support soon followed for Virtex-5 FXT and Virtex-5 TXT devices, delivering the first FPGA-based solution to be compliant with the 5Gbps version of the standard.

By leveraging all the application expertise and customer successes of its production-proven Virtex-5 FPGA PCIe solutions, Xilinx was able to achieve PCI-SIG compliance with Virtex-6 FPGAs for both PCIe 1.1 and 2.0 multi-lane configurations.

PCIe 2.0 blocks are integrated in all Virtex-6 devices with serial transceivers and are supported in all speed grades. These blocks include the complete transaction data link and physical layers, which use the Xilinx GTX transceiver technology and integrated BRAM.

The GTX serial transceivers in Virtex-6 LXT and SXT FPGAs are fully characterized across process, voltage and temperature (PVT), and the complete PCI-SIG compliance report is available for download at: www.pcisig.com/developers/compliance_program/integrators_list/pcie_2.0

The Virtex-6 FPGA Endpoint block for PCI Express also incorporates many easy-to-use features to simplify the design process, as well as configurations optimized for PCIe Endpoint and Root Port applications with additional resources to create a complete PCIe solution.