Semico releases two reports on ASIC design starts

PHOENIX, USA: Semico Research Corp. has just released two reports that provide both an historical analysis and forecasts the future of ASIC design starts.

The current global economic slowdown is having an adverse impact on design starts for ASICs. The slowing of design start activity began at the end of 2008 and is continuing through 2009. Semico believes design activity will recover back to more historical norms in 2010.

The “ASIC Design Starts: Changes in Industry Dynamics” report provides an in-depth perspective by showing a comparison between design starts for SoCs and all other types of ASICs.

This report also examines the continuing increase in SoC design costs. ASIC design starts data show changes in design for each device type including analog, mixed signal, gate array, PLD, FPGA, performance SoC, value SoC and structured ASIC.

The design starts data is further segmented by: product type, process geometry, gate count and geographic region. This report contains a wealth of data in 55 tables and 58 figures/graphs.

The “ASIC Design Starts: By Key Applications Revisited II” report segments the data by 66 of the key end applications that drive the design starts market within the computing, communications, consumer, transportation and industrial segments. Within each end application, the data is further segmented by: Analog, Mixed Signal, Performance and Value SoC, PLD, FPGA, Gate Array and Structured ASIC. This report contains an enormous amount of data in 134 tables and 69 figures/graphs.



Both reports complement each other. For each segment, they include design starts and the ASIC unit volumes associated with those design starts. While they use the same worldwide design starts information, each report analyzes the data from a different perspective.