Magma's next-gen mixed-signal design flow with new Titan release

SAN JOSE, USA: Magma Design Automation Inc. has announced a new release of the Titan(tm) mixed-signal design platform, which now includes the state-of-the art Titan Analog Simulation Environment (ASE) and Titan Schematic-Driven Layout (SDL) tools.

Several productivity enhancements have also been made to the existing Titan Schematic Editor (SE), Titan Layout Editor (LE) and Titan Shape-Based Router (SBR). With the new capabilities and enhancements, Titan delivers first-time-right, predictable mixed-signal designs, shortening the design process by weeks without sacrificing performance.

Titan is the first truly unified, open platform that embeds digital standard-cell design into the analog circuit design flow. Seamless integration with Magma's Talus digital implementation, Titan ADX accelerator, FineSim simulation and Quartz physical verification tools provides greater automation and reduces iterations during both block-level design and top-level integration.

To ease adoption, Titan natively supports OpenAccess and emerging industry standards such as the TSMC iPDK.

"Since we introduced Titan a little over a year ago we've diligently worked to deliver critical enhancements and to meet key milestones in the development of this unique platform," said Anirudh Devgan, general manager of Magma's Custom Design Business Unit.

"Our efforts have paid off. Titan has been adopted by leading semiconductor companies, qualified by the world's largest foundry for an important new initiative and even nominated for innovation awards. With the addition of the recent enhancements and Titan ASE and Titan SDL, Magma's Titan is the fastest path to mixed-signal silicon."

Titan Platform
Titan is the first full-chip mixed-signal design, analysis and verification platform. Unlike other design solutions, Titan tightly integrates mixed-signal implementation with digital implementation, circuit simulation and verification, providing comprehensive capabilities.

Titan SE, a complete and powerful schematic editor, facilitates quick schematic capture and editing, advanced search and replace, easy hierarchy traversal and design management. It has full support for buses and bundles, inherited connections and netlisting of various formats.

Titan ASE, a specification-driven, test-based analog simulation environment, empowers organized design verification across different operating conditions. Pass-fail indicators locate the failing cases and indicate final signoff with respect to the specifications. Features such as simulator-independent tests, device under text (DUT)-based test mapping help migrate the test benches across different versions of the design.

Titan SE, Titan ASE and Titan ADX capabilities are integrated to enable easy capture of the design along with the user constraints and fast verification of the optimized design with FineSim. The template-based design and organized characterization framework ease verification of the implementation generated by Titan ADX.

Titan SDL enables the creation of a connectivity-aware layout using any language pcells. Cross-probing, flyline displays during move and wiring, check and update of design data and opens and shorts locator functions minimize the physical verification loop by ensuring a layout-vs.-schematic (LVS)-correct layout.

Pattern-based device module generation accelerates the analog layout placement. Titan SDL also allows one instance to be bound to many instances between the schematic and layout.

Titan LE provides a complete set of features to accomplish full-custom layout design in fewer clicks. Its high capacity and speed coupled with the embedded Talus digital implementation capabilities provides mixed-signal chip integration within a single environment. Titan LE also provides advanced features like live-DRC, automatic guard-ring creation, net tracing, pcell abutment and interactive wire creation that includes bus routing.

Titan SBR provides constraints such as shielding, differential pair routing, star and matched routing, enabling this shape-based router to achieve highly precise analog routing results. Titan SBR can run on both the Titan and Talus database.

The Titan platform is also integrated with the Quartz DRC and Quartz LVS physical verification tools. Design rule checking (DRC) can be performed on mixed-signal designs and also run in an incremental mode to speed DRC error fixing.

FineSim Pro works with Titan to enable full-chip SPICE-level simulation and post-layout simulation with extracted parasitics.

Magma's Titan mixed-signal design platform will be available in August 2009.