Magma's Talus enables eSilicon to implement 400-million-gate designs

SAN JOSE, USA: Magma Design Automation Inc. announced that eSilicon Corp., a pioneering semiconductor value chain producer (VCP), is completing the implementation of several very large customer designs using the Talus IC implementation system, including Talus Design, Talus Vortex and Hydra.

These designs are being implemented in a 65-nanometer (nm) process and are more than 500 sq. mm in area, with more than 400 million gates. This is the equivalent of 30 million placeable objects, including more than 100 million bits of memory and more than 2,000 memory instances.

These highly complex chips require eSilicon to use a design solution with extremely high capacity and the ability to deliver fast turnaround on design planning and implementation.

In addition, given a tight delivery schedule, eSilicon needed a system that would be usable "out of the box" without a lengthy setup cycle. Magma's field team partnered with the eSilicon design team to deploy Talus.

"We selected Talus for these large designs because of its capacity and our need to minimize our deployment time and keep the implementation cycle as short as possible," said Prasad Subramaniam, vice president of Technology of eSilicon. "The high complexity of these designs poses a significant challenge in productivity and turnaround time.

"We are pleased that the Talus multi-CPU feature works smoothly and yields significant improvement across a broad implementation flow. We have our default implementation build scripts for large blocks to use two CPUs and we increased to four CPUs for critical runs. This allowed us to gain 1.5 times to 3 times improvement in turnaround time on these large designs."

eSilicon found Talus to be well suited for these designs. Talus' underlying unified data model architecture contains the entire set of data associated with the design. The complete design data can be exported or imported at any time as a Volcano(tm), Magma's proprietary database format.

One of the eSilicon designs is based on a collaborative development model with the customer, and Talus' unified architecture simplifies the efficient handoff of design data via Volcanoes at various points during the implementation process.

In addition, Talus' core multi-CPU feature and enhanced GlassBox modeling for timing enabled very significant improvement in the turnaround times for implementation and analysis.

One key challenge for these complex chips is the turnaround times for top-level analysis and optimization. eSilicon is making extensive use of a new Hydra GlassBox abstraction capability.

This enhanced GlassBox abstraction feature yields extremely compact representations of the blocks that contain all the physical, timing and extraction data necessary for fast and accurate chip-level analysis and optimization without consuming enormous amounts of memory.

Because of this new "cached delay" feature for GlassBox abstraction, the latest Talus release requires less than 50 percent of the memory resources required by the previous Talus version and delivers up to a 5X improvement in runtime compared to the previous GlassBox approach.

"The fast deployment of Talus and implementation of these designs is a testament to eSilicon's engineering skill and demonstrates Talus' ability to handle large, complex designs," said Premal Buch, general manager of Magma's Design Implementation Business Unit.

"The size of these designs and the speed of deployment demonstrate the major improvements in capacity, runtime and usability that have been engineered into the latest Talus release. It also validates Hydra's capability for managing the top-level design and optimization of very large designs without excessive memory consumption."