TSMC, Synopsys ally on interoperable unified physical verification formats

MOUNTAIN VIEW, USA: Synopsys Inc. announced that its recently launched IC Validator DRC/LVS product now fully supports interoperable Design Rule Checking (iDRC) and Layout-Versus-Schematic (iLVS), the new TSMC unified physical verification formats.

Synopsys was one of the first EDA suppliers to collaborate with TSMC to create and develop the unified formats, transitioning from a vendor-specific to an interoperable specification of technology files, which not only enables consistent interpretation across all tools, but also assures timely access to all Synopsys customers.

"Working with advanced node customers, TSMC and Synopsys concluded that a unified specification for Physical Verification tools was key to accelerating time to market, a primary benefit of TSMC's Open Innovation Platform," said S.T. Juang, senior director of Design Infrastructure Marketing at TSMC.

"We benefited from the close cooperation with Synopsys, using IC Validator as the development and validation platform and a catalyst for the timely introduction of these formats."

IC Validator was used from early on as one of the reference platforms for prototype development and final qualification of the unified formats. Architected to deliver the high accuracy necessary for leading-edge process nodes, superior scalability for efficient utilization of available hardware, and ease-of-use, IC Validator provides a step up in physical designer productivity.

IC Validator delivers speed-up through multicore processors by efficiently parsing iDRC/iLVS generic rules into atomic instructions suitable for highly distributed execution.

In addition, with its advanced and near linear scalar hybrid signoff engine, IC Validator provides an efficient platform for coding and validating complex polygon and edge based rules needed for emerging process nodes.

As part of the Galaxy Implementation Platform, IC Validator is an ideal add-on to IC Compiler for In-Design physical verification, enabling place and route engineers to accelerate time to tape-out and improve manufacturability by performing physical verification within the implementation flow.

It is production-ready and has been successfully used for tape-outs at leading fabless customers and chip manufacturers. Synopsys will showcase iDRC- and iLVS-enabled flows with IC Validator at the 46th Design Automation Conference in San Francisco, California.

"By eliminating qualification and consistency barriers and assuring timely access to technology files, this close collaboration between TSMC and Synopsys, with participation from other EDA vendors, clears the way for designers to easily select amongst available physical verification tools," said Bijan Kiani, vice president of product marketing, design and manufacturing products at Synopsys.

"This puts Synopsys in a strong position to efficiently bring In-Design physical verification to our common customers."