ST unveils latest advances in design methodologies at DAC 2009

SINGAPORE: STMicroelectronics will participate as presenter or co-author of several papers at the DAC 2009 (Design Automation Conference), which takes place from July 26-31, 2009, in San Francisco, California.

ST’s contributions to the conference cover advances in design methodologies and automation in the areas of 3-D stacking for complex SoC (System-on-Chip) ICs, physical- and system-level chip design, and IC reliability.

In the DAC 2009 ‘Management Day’ session, Philippe Magarshack, STMicroelectronics’ General Manager of Central CAD & Design Solutions will present: ‘3-D Stacking: Opportunities and Trends for Consumer SOCs’, which will discuss 3-D integration as a promising technology to extend the momentum of Moore’s Law into the next decade, offering higher transistor density, faster interconnects, heterogeneous technology integration, with potentially lower power, cost and faster time-to-market.

However, 3-D integration isn’t without challenges: the presentation discusses the need for a range of new capabilities including process technology, architectures, design methods and tools, and manufacturing-worthy test solutions to be developed before 3-D chips can be mass produced for consumer applications.

Also, as part of the Management Day, Magarshack will participate on the panel ‘Making Critical Decisions for Emerging SoC Development,’ which will discuss emerging solutions for complex nanometer SoCs and their economic impact.

ST is also presenting several papers in physical and system-level design, including the examination of architectural-level design and power-estimation techniques, and the design-automation of IP re-use.

The need to design differentiated SoC product derivatives in extremely narrow time windows is tackled by a paper from ST engineers. The paper describes the moving of design creation to higher levels of abstraction, presenting an ESL (Electronic System Level) design methodology as a solution to deal with the increasing design challenges in the industry. In addition, the paper explores solutions for optimal designs in terms of power performance and silicon die area.

Another paper describes how ST engineers have used the SPIRIT (Structure for Packaging, Integrating and Re-using IP within Tool flows) Consortium’s IP-XACT standards to enable IP reuse through design automation, to provide an SoC integration solution for ST’s program (with Freescale) for the fast development of new 32-bit automotive microcontroller families.

An approach to improving design productivity for digital consumer ICs is the subject of another paper. ST’s engineers propose allowing front-end designers to prototype the SoC at the architecture level, gaining early insight into potential implementation issues during the design capture stage.

Power management, also, is an increasingly important concern for both wireless and wired applications. ST engineers will present an architectural-level power planning and estimation system to manage the challenges to preserve power and extend battery life in portable products.

Testing and reliability are also addressed by ST’s engineers, in two papers. The first paper is a presentation on a low-power DFT (Design-For-Test) flow for multi-voltage designs and ATPG (Automatic Test Pattern Generation).

The second paper examines an approach for the reduction of EMI (Electromagnetic Interference) to produce very robust automotive IC designs.