Azuro's low-power CTS for complex SoC designs

Design Automation Conference 2009, SANTA CLARA, USA: Azuro Inc., a provider of advanced implementation tools for nanometer chip design, has announced version 5 of its PowerCentric low-power clock tree synthesis (CTS) solution with extended support for complex system-on-chip (SoC) designs.

“Azuro’s proprietary global approaches to clock tree balancing and patented clock gate optimization algorithms are ideally suited to complex SoC designs,” said Paul Cunningham, CEO and co-founder of Azuro.

“PowerCentric is being actively used to tape out many of the world’s most complex chips with hundreds of intertwined clocks and dozens of voltage islands. This latest software release strengthens our proven leadership position in CTS and reinforces Azuro’s continued commitment to deliver lowest clock power, best clock gate timing, and fastest CTS turnaround time.”

Key features in PowerCentric version 5 include:

* 30 percent reduction in CTS runtimes on designs with multiple modes and corners.
* Enhanced clock gate optimization and clock tree buffering algorithms delivering up to 10 percent additional clock power savings.
* Comprehensive support for UPF 2.0 (IEEE 1801) power domain configuration format.
* Ground breaking new “Trial CTS” capability delivering accurate post-CTS design timing with runtimes of less than one hour per one million placeable instances.
* Top level clock balancing through hardened sub-chips with back-annotated parasitics.
* Full database save with rapid restore.

PowerCentric version 5 is available now with UPF 2.0 support in limited availability.