Design Automation Conference 2009, SANTA CLARA, USA: Enabling electronic system level (ESL) design flows for increasingly complex system on a chip (SOC) devices, Calypto Design Systems Inc. announced the release of SLEC 4.0, the latest version of its popular sequential logic equivalence checking (SLEC) product family.
SLEC is the semiconductor industry’s only comprehensive functional verification solution that formally verifies equivalence between ESL models and RTL implementations. The new version has up to five times the capacity of the previous version and provides tighter integration with the leading high-level synthesis (HLS) tools from Cadence Design Systems, Mentor Graphics, and Forte.
“HLS tools are becoming more efficient at handling larger functions. As a result, customers are applying HLS tools to design blocks with significant complexity, especially from a sequential perspective,” said Tom Sandoval, CEO of Calypto Design Systems.
“SLEC 4.0 keeps pace with the most sophisticated designs and provides an automated path to comprehensive verification with the industry’s only proven sequential equivalence checker. With SLEC, designers can avoid running time-consuming simulations and can uncover bugs that might otherwise go undetected and cause catastrophic delays to product development timelines.”
Calypto pioneered sequential logic equivalence checking when it announced its first version of SLEC nearly five years ago. Since that time, SLEC’s capacity has grown from thousand-gate blocks and tens of cycles of sequential complexity to hundreds of thousands of gates and thousands of cycles of sequential complexity.
The verification challenges have increased exponentially with these more sophisticated functions, making traditional simulation-based verification even less effective.
Optimized database and improved integration with HLS tools
Featuring algorithmic enhancements to Calypto’s patented word level solvers, the latest version of SLEC also includes dramatic improvement to SLEC’s proprietary database that results in a reduced memory footprint while SLEC is running. Together, these advancements enable the tool to handle larger, more complex designs.
As a result, designers can more freely use high level synthesis for the generation of highly complex functions, knowing that SLEC can provide comprehensive verification. The interface between SLEC and the leading HLS tools — Mentor Catapult, Cadence C-to-Silicon compiler, and Forte Cynthesizer — has also been improved in SLEC 4.0 to ensure an automated, efficient path to formal verification, requiring little or no user intervention.
Multiple clock support added
The ability to handle multiple clock designs has traditionally been a limitation with sequential logic equivalence checking. As SLEC capacity has increased, allowing the tool to support larger and more complex graphics, networking, multimedia, and wireless functions, the need to comprehensively verify designs with multiple clocks has become more and more prevalent.
With version 4.0, SLEC customers can now fully verify designs with multiple, independent clocks. For example, SLEC RTL can verify that the relationship between two clocks -- e.g., one clock is a multiple of another) is not disrupted by the manual introduction of sequential optimizations for power or performance by a designer. SLEC RTL can also now detect the illegal mixing of signals from different clock domains introduced by sequential transformations.
The SLEC family of products includes:
* SLEC System: Formally verifies equivalence of system-level models and RTL designs.
* SLEC System-HLS: Formally verifies that an RTL design generated using high-level synthesis is functionally equivalent to its corresponding system level model.
* SLEC RTL: Formally ensures functional equivalence between a golden RTL model and a corresponding RTL model has been sequentially modified to reduce power or improve performance.
* SLEC Pro: Comprehensively verifies that an RTL design generated by Calypto’s PowerPro product is functionally equivalent to its corresponding golden RTL model.
* SLEC 4.0 Showcased at 2009 DAC, Calypto to Present and Co-host Luncheon.