Atrenta, Mentor Graphics ally on power optimization for high-level synthesis

Design Automation Conference 2009, SAN JOSE, USA: Atrenta Inc. a leading provider of Early Design Closure solutions to radically improve design efficiency throughout the IC design flow, announced a collaboration with Mentor Graphics Corp. on an high-level synthesis power optimization flow.

The collaboration between the two companies has resulted in an interface between Mentor’s Catapult C Synthesis high-level synthesis tool and Atrenta’s SpyGlass-Power RTL power estimation and reduction tool to automate multi-level clock gating, an important technique used by designers in low-power designs.

According to Mentor Graphics, Catapult is the industry’s leading high-level synthesis tool and offers the fastest path to verified RTL from pure C++. With its new low-power optimizations, Catapult will thoroughly analyze the design to determine gateable clocks and build the appropriate logic -- an often error-prone and tedious task when done manually at the backend of the design flow. This new technology delivers near 100 percent perfect clock gating.

The resulting RTL output from Catapult is then seamlessly handed off to SpyGlass-Power, which examines every clock gating candidate identified by Catapult, measures the potential power savings, and determines which particular candidates should be included or excluded from the clock gating insertion process.

The static and dynamic power estimates from SpyGlass-Power are fed back into Catapult C for performance, area and power tradeoff analysis, and the resulting RTL netlist is then available to downstream RTL synthesis tools, resulting in a very efficient low-power design implementation.

According to Mentor Graphics, dynamic power savings for clock gating is design and test vector dependent, however measurements on more than 300 customer designs showed improvements ranging from 10 to 90 percent with an average improvement of 40 percent.

“By using a power-aware high-level synthesis flow starting from C++, designers have at their disposal a design methodology that makes power consumption a key design metric right at the start of the design process, where it can have the maximum impact,” said Shawn McCloud, product line director for High-Level Products at Mentor Graphics.

“The collaboration with Atrenta and their SpyGlass product significantly enhances the flow by quantifying power savings and ensuring that the generated RTL is power optimized.”

“The collaboration with Mentor and Catapult C provides users of high-level synthesis with the benefits of RTL analysis and optimization from our SpyGlass platform, especially for power estimation and reduction,” said Kiran Vittal, product marketing director of power and test products at Atrenta. “Power optimization is an important focus area for Atrenta. Several new capabilities to support better power optimization will be announced in the coming months.”

Atrenta and Mentor Graphics will showcase the results of this collaboration in a joint demonstration of an ESL-to-RTL power optimization flow in Atrenta’s booth at the 46th Design Automation Conference (DAC) in San Francisco.

The Catapult/SpyGlass flow is available now. The respective tools can be purchased from Mentor Graphics and Atrenta.