Sigrity partners with TSMC on Reference Flow 12.0

CAMPBELL, USA: Sigrity, Inc., the market leader in signal and power integrity solutions, announced that TSMC has included two additional Sigrity analysis products – XcitePI and PowerSI – in its new TSMC Reference Flow 12.0 targeting TSMC’s 28 nanometer process.

XcitePI creates chip electrical models and performs chip-centric co-simulation to ensure ICs will function properly in electronic systems. PowerSI can be used in combination with XcitePI for chip/system co-design while also performing fast electrical analysis of IC packages and printed circuit boards to overcome increasingly challenging and interrelated power, signal and EMI issues. These products join Sigrity’s XtractIM, OrbitIO and OptimizePI products, which were added previously and continue to be supported in the TSMC reference flow. These products will be featured in Sigrity’s booth (#2525) at this year’s Design Automation Conference in San Diego, Calif., June 5-10, 2011.

Companies that rely on TSMC flow support benefit from streamlined chip and system-level analysis utilizing Sigrity solutions for a broad range of design types, including SiP and 3D IC implementations. Robust chip/system co-simulation options avoid performance and reliability risks, streamlining time to market.

“Sigrity’s electromagnetic analysis tools enable designers to identify potential reliability risks early, when they can be quickly resolved,” said Suk Lee, director of design infrastructure marketing, TSMC. “Sigrity’s tool suite offers excellent accuracy and the company’s expertise is especially valuable in tackling challenges associated with 2.5D and 3D IC designs.”

Both TSMC and Sigrity have been active in developing solutions to support the growing need for 2.5D and 3D IC design, extraction and analysis solutions. 2.5D designs include silicon interposers to accommodate interconnections among multiple chips. The silicon interposers deliver high performance without the extra costs associated with 3D IC implementations or full SoC designs; they also provide excellent opportunities for efficient IP reuse and optimized design partitioning across multiple chips, including those with different process nodes.

3D IC designs include a mixed vertical stack with through-silicon-via (TSV) connections. 2.5D and 3D IC design approaches build on SiP concepts and benefit from Sigrity’s longstanding support for multi-die package flows. For 3D IC projects, TSV structures require simulation with all relevant effects including inductance, mutual inductance and capacitance. Sigrity offers the accuracy needed for chip/system co-simulation and capabilities to automate the model connections required for these complex designs.

“TSMC is recognized both for IC manufacturing leadership and for its emphasis on practical design flow guidance for complex semiconductor products,” said Dr. Jiayuan Fang, president, Sigrity, Inc. “Our collaboration with TSMC extends technology capabilities for customers involved with both mainstream designs and innovative 3D IC projects.”

Sigrity’s XcitePI, PowerSI, XtractIM, OrbitIO and OptimizePI products are included in the TSMC Reference Flow 12.0 support.

* XcitePI provides die IO and power delivery electrical models along with a chip-centric co-simulation environment for time domain (transient waveforms) and frequency domain (impedance) to characterize chip/package/board systems. A wizard-driven interface generates pre-layout die power models in advance of GDSII and LEF/DEF availability to produce SPICE-compatible electrical models. XcitePI readily handles 3D IC simulations including projects with silicon interposers, stacked die and TSVs.

* PowerSI provides system-centric frequency domain simulation. Highly accurate electrical models can be generated with PowerSI that include realistic system impacts. This accuracy is essential in identifying the combined effects of signal integrity, power integrity and EMI. PowerSI and XcitePI work together for chip/system co-simulation applications.

* XtractIM provides package electrical model extraction combined with an intuitive and comprehensive assessment of IC package performance to efficiently identify potential problems. It supports all package types, including single-die ball grid arrays (BGAs), leadframe packages and multi-die SiP implementations with accurate modeling of wirebond and flip-chip interconnect. The package model extraction capability in XtractIM produces lower frequency IBIS and SPICE models as well as broadband accurate models that can be easily connected to chip and board models for chip/system signal- and power-integrity analysis.

* OrbitIO supports multi-substrate planning of die, interposers, packages and printed circuit boards, enabling the development and optimization of device placement and connectivity within a full system context. It simplifies chip-level IO pad ring design, die placement, bump pattern generation, TSV placement and RDL routing to support the planning and development of 2.5D systems, stacked 3D ICs as well as traditional packages and SiPs with stacked and flat configurations.

* OptimizePI is focused on power delivery system improvement with a high degree of automation to support IC package and system-level decoupling capacitor optimization. Chip-level power delivery models can be incorporated for automatic performance and cost optimization of the total design across the chip, package and system to efficiently meet customer targets for power delivery network impedance.