Synopsys and TSMC to deliver custom design solution for 28nm analog/mixed-signal Reference Flow 2.0

MOUNTAIN VIEW, USA: Synopsys Inc. has collaborated with TSMC to deliver Synopsys' custom design solution for TSMC's 28-nanometer (nm) Analog/Mixed-Signal (AMS) Reference Flow 2.0. Part of TSMC's comprehensive 28nm design infrastructure, the flow delivers new advanced automation capabilities to improve productivity and shorten the design cycle. The new capabilities include both parasitic-aware and Layout Dependent Effect (LDE)-aware design methodologies.

"The AMS Reference Flow 2.0 delivers new analog/mixed-signal design automation capabilities for advanced process nodes," said Suk Lee, director of design infrastructure marketing at TSMC. "Custom Designer's environment provides a platform for rapidly developing new design capabilities and integrating TSMC advanced process technology."

Synopsys' comprehensive custom solution was validated for TSMC's AMS Reference Flow 2.0 to help ensure that customers can be more confident in meeting their design quality and timeline requirements. Key components of the solution are Galaxy Custom Designer custom implementation, HSPICE circuit simulation, CustomSim FastSPICE circuit simulation, Custom WaveView waveform analyzer, IC Validator physical verification and StarRC™ Custom parasitic extraction.

"By collaborating with TSMC, we help ensure that our mutual customers have access to a proven and productive custom IC design solution that has been verified by both companies to address 28-nanometer design challenges," said Bijan Kiani, vice president of product marketing at Synopsys. "The combination of TSMC's and Synopsys' respective expertise in process technology and design automations helps to more rapidly deliver innovative solutions to the marketplace."

Parasitic aware
The parasitic-aware flow reduces the number of late-stage design and layout iterations due to parasitic effects by accurately estimating pre-layout interconnect parasitics using process-based models. Additionally, interconnect parasitic constraints can also be specified in the schematic and then automatically verified in the layout.

"What-if" analysis on completed layouts is also supported. This capability enables designers to easily analyze the effects of transistor parameter changes without modifying the layout and taking into account the actual layout interconnect parasitics.

LDE aware
The LDE-aware capability helps accelerate the layout process by reducing design iterations to accommodate LDE. This method allows designers to model the layout-dependent effects during the initial pre-layout design phase and accelerate time-to-tapeout.