MHEG-5 is an open standard middleware solution, an application program interface (API), designed specifically for low-cost memory constrained devices -- particularly suitable for digital interactive TV (iTV) services and is platform agnostic. Simply put, MHEG-5 is a simple object-orientated programming language.
MHEG-5 was initially adopted in 1998 by ONDigital in the United Kingdom (rebranded as ITV Digital) for use in the world’s first pay-TV digital terrestrial television (DTT) network. ONDigital lead the industry wide specification and development task of the first MHEG-5 profile, which subsequently (after the collapse of ITVDigital) formed the basis for deployment of interactive services on the UK DTT platform (Freeview).
Developed by the ISO-MHEG group and DAVIC in 1995, it is intended as a UI for DAVIC interactive services and VOD. MHEG-5 has been standardized in ISO 13522-5 and adopted by the UK DTG in 1997.
Going by its history on IMPALA (The International MHEG Promotion Alliance), MHEG (Multimedia and Hypermedia information coding Expert Group) originally developed and standardized by Working Group 12 (WG12) of the ISO -- officially known as ISO/IEC JTC1/SC29/WG12. It was developed in the mid 1990s as part of the DAVIC (Digital Audio Video Council) standardization effort to support interactivity and navigation of multimedia services on various small footprint devices.
WG12 issued a suite of documents (MHEG parts 1-8) as part of MHEG standard covering extensions for scripting language (MHEG-6), testing and interoperability (MHEG-7) and support for encodings in XML format (MHEG-8). Part 5 of the standard, officially known an ISO/IEC 13522-5, or more commonly know as MHEG-5 that is of primary relevance to interactive DTV.
So what's hot about MHEG-5? Well, the standard's profile evolved to UK Profile 1.06 (current); ETSI standard ES 202184. And now, new international profiles extend the UK profile. These include: New Zealand -- extra Maori characters and EPG key; Hong Kong -- Traditional Chinese font; Singapore/China - simplified Chinese font. Certain other extensions are said to be under development within DTG for possible deployment in 2008. These include IP interaction channel (return path), improved graphics, HD compatibility and support, and PVR support.
Heading for India?
What's more significant is that MHEG-5 is said to be launching in India and in Hong Kong in 2008! Trials and evaluations are reportedly ongoing in Ireland, Malaysia, Singapore, Turkey, India and Russia. There is said to be interest from other countries in Europe and Asia as well.
MHEG-5 has no known essential IPR. The MHEG middleware software is typically less than US$1 per receiver. It has had wide integration into iDTVs in Europe. Finally, MHEG is proposed as the UI for new Common Interface spec (CI+), as well.
I hope to be speaking with IMPALA sometime soon about its plans for India and update you appropriately!
Thursday, March 27, 2008
Friday, March 21, 2008
Will the solar bubble really burst in 2009?
Will this actually happen? Will the solar bubble burst in 2009 as supply exceeds demand? I don't know, but I came across this news and am pleased to share with you.
According to Lux Research, the overall solar industry revenues will grow to $70.9 billion in 2012, but oversupply and new technologies will squeeze today’s leaders! This has been reported in its new report titled "Solar State of the Market Q1 2008: The End of the Beginning."
As per Lux Research's study, the solar industry has been having a remarkable run, attracting the attention of all stakeholders. However, all of this activity has also led to the growth of a bubble, which will most likely burst some time soon.
Lux Research says that while growth will continue to be robust -- solar industry revenues will grow at a brisk 27 percent annual rate to reach $70.9 billion in 2012, up from $21.2 billion in 2007 -- the solar industry will look very different just two years from now!
"Government subsidies in countries like Japan, Germany, and Spain have helped make large-scale solar a reality, with annual installations reaching 3.43GW in 2007," said Lux Research Senior Analyst Ted Sullivan, the report’s lead author. "During this period, solar demand has consistently outpaced supply. But the market is now approaching a tipping point. We project that the supply of solar modules will exceed demand in 2009, leading to falling prices and a shake-out among companies that aren’t prepared to thrive in this new environment -– particularly crystalline silicon players that haven’t invested in new thin-film technologies."
Interesting comments! At the recently concluded ISA's Vision Summit, it was disclosed by Jairam Ramesh, union minister of state for Commerce, that the Indian government had received seven confirmed investments in the Hyderabad Fab city, with a total value of $7 billion for 10 years.
Five firms have been given principle approval with $1 billion investment. Proposals of three other firms -- Videocon, Moser Baer, and Hindustan Semicon Manufacturing Corporation (HSMC), have yet to be considered.
Reliance is said to have put forward a proposal for solar/PV manufacturing facility with an investment of $5 billion in Jamnanagar. This proposal is under consideration. The majority of firms proposed to set up in Fab city are mainly focused on solar/PV.
As I said in that blog, the last bit is the interesting part. If everyone focuses on solar/PV, who will focus on the other ancillaries required to complete the semicon ecosystem? What about the LCD, OLED plants, etc., that were mentioned in the semiconductor policy? Now, with the Lux Research report predicting a squeeze next year, these Indian companies investing in solar/PV fabs need to be careful about how they go about setting up their businesses.
The solar business will surely be a space worth watching over the coming years!
According to Lux Research, the overall solar industry revenues will grow to $70.9 billion in 2012, but oversupply and new technologies will squeeze today’s leaders! This has been reported in its new report titled "Solar State of the Market Q1 2008: The End of the Beginning."
As per Lux Research's study, the solar industry has been having a remarkable run, attracting the attention of all stakeholders. However, all of this activity has also led to the growth of a bubble, which will most likely burst some time soon.
Lux Research says that while growth will continue to be robust -- solar industry revenues will grow at a brisk 27 percent annual rate to reach $70.9 billion in 2012, up from $21.2 billion in 2007 -- the solar industry will look very different just two years from now!
"Government subsidies in countries like Japan, Germany, and Spain have helped make large-scale solar a reality, with annual installations reaching 3.43GW in 2007," said Lux Research Senior Analyst Ted Sullivan, the report’s lead author. "During this period, solar demand has consistently outpaced supply. But the market is now approaching a tipping point. We project that the supply of solar modules will exceed demand in 2009, leading to falling prices and a shake-out among companies that aren’t prepared to thrive in this new environment -– particularly crystalline silicon players that haven’t invested in new thin-film technologies."
Interesting comments! At the recently concluded ISA's Vision Summit, it was disclosed by Jairam Ramesh, union minister of state for Commerce, that the Indian government had received seven confirmed investments in the Hyderabad Fab city, with a total value of $7 billion for 10 years.
Five firms have been given principle approval with $1 billion investment. Proposals of three other firms -- Videocon, Moser Baer, and Hindustan Semicon Manufacturing Corporation (HSMC), have yet to be considered.
Reliance is said to have put forward a proposal for solar/PV manufacturing facility with an investment of $5 billion in Jamnanagar. This proposal is under consideration. The majority of firms proposed to set up in Fab city are mainly focused on solar/PV.
As I said in that blog, the last bit is the interesting part. If everyone focuses on solar/PV, who will focus on the other ancillaries required to complete the semicon ecosystem? What about the LCD, OLED plants, etc., that were mentioned in the semiconductor policy? Now, with the Lux Research report predicting a squeeze next year, these Indian companies investing in solar/PV fabs need to be careful about how they go about setting up their businesses.
The solar business will surely be a space worth watching over the coming years!
Thursday, March 20, 2008
Top 25 semicon vendors of 2007
Here are the top 25 global suppliers of semiconductors, according to iSuppli. First up, there are no surprises in the top 5 -- Intel, Samsung, Texas Instruments, Toshiba and STMicroelectronics retain their spots for this year too. The surprises occur in the second rung -- or, in the next five spots.Renasas and Hynix exchanged places, with Hynix moving up from 7th position in 2006 to 6th position in 2007, and Renasas dropping from 6th last year to 7th. This is very interesting, because, despite memory market pains during 2007, South Korea's Hynix Semiconductor and Japan's Toshiba and Elpida Memory achieved memory-chip revenue growth of 15, 14.5 and 8.8 percent respectively in 2007, as per iSuppli.
Infineon, Sony major movers
The next three positions are the major surprises of the year. Well, the 10th position was no surprise to me -- AMD, dropping from 8th in 2006 to 10th in 2007. Sony and Germany's Infineon Technologies have been the biggest gainers of the year!
According to iSuppli, Infineon acquired TI's DSL CPE chip business and its wireless baseband semiconductor unit, boosting its revenue. Qimonda, which spun off Infineon, dropped from 12th in 2006 to 16th this year. This split had seen Infineon go out of the top 10 last year.
As per iSuppli, logic application specific integrated circuits (application specific standard products and ASICs) enjoyed the strongest performance among all semicon segments in 2007. Sony and Toshiba were key drivers of growth in this segment due to their sales of semiconductors for the PS3.
Fabless is surely in
The presence of Qualcomm and nVidia in the top 25 list speaks volumes of the power of fabless companies. Qualcomm moved up from 16th to 13th position this year, while nVidia moved up from 25th to the 20th position this year. There is every chance that we will see a fabless company in the top 10 next year! There is an even better chance that more fabless companies will make it to the top 25 companies next year and in future.
All other key players dropped in their rankings. NXP dropped from 9th to 11th; NEC dropped from 11th to 12th; Freescale from 10th to 14th; Micron from 13th to 15th; Elpida moved up from 19th to 17th; while Matsushita and Broadcom dropped a place each.
An iSuppli release says: "Overall, the top 25 semiconductor suppliers significantly outperformed the combined performance of companies ranked lower than them in 2007. The Top-25 as a group achieved revenue growth of 4.5 percent in 2007 while the combined growth of all other semiconductor suppliers was only 0.8 percent."
On a personal note, I would love to see names like SemIndia and HSMC making it to the list. If not now, then at least sometime in the near future. However, it seems from certain published reports that the Indian fab story has gone all wrong. I'll take up this topic in a future blog for sure!
Saturday, March 15, 2008
NXP India achieves RF CMOS in single chip
NXP Semiconductors India has developed the PNX4902, an ultra low-cost GSM/GPRS single chip, which was announced this February. The highlight -- the entire analog and RF work done has been in Bangalore! You might wonder what's so unique about this!
Well, let's start with what is tough about RF CMOS in single chip! CMOS is primarily a digital process. The analog circuit design in CMOS is tough, and the RF circuit design in CMOS is even tougher. Now, the co-existence of RF CMOS circuits with noisy digital in a single chip was (and is) considered the holy grail of chip design.
Next, cellular standards (such as GSM, EDGE) and specs are much tougher than other comparable standards like FM, Bluetooth, etc. Also, some key cellular parameters like RX sensitivity become tougher for single chips aimed at emerging markets. Especially, we all know that base stations are sparse in rural areas. Taking all of these as a whole -- RF design in presence of digital noise is the biggest challenge in a single chip!
Factors enabling single chip design
There are said to be three factors. One, RF CMOS is the high quality analog/RF design in CMOS. The high-performance RF blocks like LNA, mixers, etc., used to be the domain of BiCMOS, a higher cost technology. Next, fine-line CMOS (0.18mm and lower) provide high fT and lower noise.
Two, there are new architectures that minimize analog signal processing. Chip designers to convert the analog signal to digital -- so they might as well do it early -- analog-to-digital conversion at the IF, instead of at DC. There's also a need to move the final down-conversion and filtering into digital domain.
Three, the use of DSP to calibrate the analog performance. Things like temperature and process sensitivities in analog circuits need adjustments. Also, the digital engines can provide the ability to 'lock-in' the performance. Finally, a strong 'engineering culture' is a MUST to execute on complex chips.
Factors enabling AeroFone single chip design
NXP had acquired Silicon Labs Wireless group in 2007. Silicon Labs was a leader in RF CMOS, and so it also acquired numerous patents and trade secrets. Trade secrets for integration of RF CMOS circuits with noisy digital provide an edge over competitors as the integration intensifies.
Thereafter, NXP went on to form the NXP India single-chip design team. As single chip products are designed for emerging economies, NXP India invested heavily to develop the design expertise in Bangalore. The seed group of chip leads and system leads relocated from USA to India to start an analog/RF competency center for developing highly integrated chips.
The NXP India single chip design team has the vision to be the best center of competence in architecture and design of highly integrated circuits (ICs) for emerging market products. It is building the best analog/RF group in India.
Well, let's start with what is tough about RF CMOS in single chip! CMOS is primarily a digital process. The analog circuit design in CMOS is tough, and the RF circuit design in CMOS is even tougher. Now, the co-existence of RF CMOS circuits with noisy digital in a single chip was (and is) considered the holy grail of chip design.
Next, cellular standards (such as GSM, EDGE) and specs are much tougher than other comparable standards like FM, Bluetooth, etc. Also, some key cellular parameters like RX sensitivity become tougher for single chips aimed at emerging markets. Especially, we all know that base stations are sparse in rural areas. Taking all of these as a whole -- RF design in presence of digital noise is the biggest challenge in a single chip!
Factors enabling single chip design
There are said to be three factors. One, RF CMOS is the high quality analog/RF design in CMOS. The high-performance RF blocks like LNA, mixers, etc., used to be the domain of BiCMOS, a higher cost technology. Next, fine-line CMOS (0.18mm and lower) provide high fT and lower noise.
Two, there are new architectures that minimize analog signal processing. Chip designers to convert the analog signal to digital -- so they might as well do it early -- analog-to-digital conversion at the IF, instead of at DC. There's also a need to move the final down-conversion and filtering into digital domain.
Three, the use of DSP to calibrate the analog performance. Things like temperature and process sensitivities in analog circuits need adjustments. Also, the digital engines can provide the ability to 'lock-in' the performance. Finally, a strong 'engineering culture' is a MUST to execute on complex chips.
Factors enabling AeroFone single chip design
NXP had acquired Silicon Labs Wireless group in 2007. Silicon Labs was a leader in RF CMOS, and so it also acquired numerous patents and trade secrets. Trade secrets for integration of RF CMOS circuits with noisy digital provide an edge over competitors as the integration intensifies.
Thereafter, NXP went on to form the NXP India single-chip design team. As single chip products are designed for emerging economies, NXP India invested heavily to develop the design expertise in Bangalore. The seed group of chip leads and system leads relocated from USA to India to start an analog/RF competency center for developing highly integrated chips.
The NXP India single chip design team has the vision to be the best center of competence in architecture and design of highly integrated circuits (ICs) for emerging market products. It is building the best analog/RF group in India.
Wednesday, March 12, 2008
VLSI as a career in India
It is a great pleasure to find people, most of whom I don't even know, either leave comments on my blog, or even leave a post asking for help. First of all, I would like to thank all of those who read my blog posts. Two, I would like to thank a reader, Paul, for his best wishes pertaining to my recovery. Thank you friend!
I would also like to address a query left by a young reader R. Shrivatsan. It is my pleasure to let you all know that he is going to do a PG course in VLSI in Bangalore. There are lot of opportunities in the VLSI space in the country, and it would do India a lot of good if more such youngsters took to this line. India needs people with experience in VLSI!
I am not a career consultant, nor am I qualified enough to give VLSI tips to people. However, I will try and list some sites who can offer that kind of guidance to people interested in VLSI as a career.
A very good place to start looking for VLSI related information is the VLSI Society of India. This is the site that covers all that is related to VLSI. There are some related sites as well, and I am sure it would help those interested in pursuing VLSI as a career. The India Semiconductor Association is also a good place to ask around for VLSI related information.
I'd like to add that the VLSI Society of India signed an MoU with the Visweswaraya Technological University (Belgaum, Karnataka) and the India Semiconductor Association in June 2005 to spread and improve the quality of VLSI education. Under the aegis of this MoU, colleges that offer M.Tech programs in VLSI Design and Embedded Systems have been identified as centers where champions from the industry will work in close cooperation with faculty champions to improve the quality of M.Tech programs.
I also came across certain sites offering some valuable information. The VLSI Chip Design site lists some of the leading ASIC and VLSI design companies in India. Then, there is this nice little blog -- India VLSI -- which also has some good indications as far as VLSI companies in India are concerned.
Next, there's a nice site -- VLSI Chip Design -- which also offers lots of answers, as well as news, jobs and views about the semiconductor industry in India.
Further, there a host of very good verification companies in India, such as EVE, Tessolve, etc. Lot of work is going on in this space as well. I also came across EDA 101 -- a new community for electronic design engineers, managers, students and consultants whose career includes use or management of Electronic Design Automation (EDA) tools in modern digital and analog design.
There is lot of information going around on opportunities in VLSI in India. My best wishes to Shrivatsan, and hope that India gets a great VLSI engineer.
Lastly, I would like to invite knowledgeable people to send me links, etc. on any good sites, education institutes in India, pertaining to VLSI. I will publish the links and information on my blog and also acknowledge those people. Many thanks!
I would also like to address a query left by a young reader R. Shrivatsan. It is my pleasure to let you all know that he is going to do a PG course in VLSI in Bangalore. There are lot of opportunities in the VLSI space in the country, and it would do India a lot of good if more such youngsters took to this line. India needs people with experience in VLSI!
I am not a career consultant, nor am I qualified enough to give VLSI tips to people. However, I will try and list some sites who can offer that kind of guidance to people interested in VLSI as a career.
A very good place to start looking for VLSI related information is the VLSI Society of India. This is the site that covers all that is related to VLSI. There are some related sites as well, and I am sure it would help those interested in pursuing VLSI as a career. The India Semiconductor Association is also a good place to ask around for VLSI related information.
I'd like to add that the VLSI Society of India signed an MoU with the Visweswaraya Technological University (Belgaum, Karnataka) and the India Semiconductor Association in June 2005 to spread and improve the quality of VLSI education. Under the aegis of this MoU, colleges that offer M.Tech programs in VLSI Design and Embedded Systems have been identified as centers where champions from the industry will work in close cooperation with faculty champions to improve the quality of M.Tech programs.
I also came across certain sites offering some valuable information. The VLSI Chip Design site lists some of the leading ASIC and VLSI design companies in India. Then, there is this nice little blog -- India VLSI -- which also has some good indications as far as VLSI companies in India are concerned.
Next, there's a nice site -- VLSI Chip Design -- which also offers lots of answers, as well as news, jobs and views about the semiconductor industry in India.
Further, there a host of very good verification companies in India, such as EVE, Tessolve, etc. Lot of work is going on in this space as well. I also came across EDA 101 -- a new community for electronic design engineers, managers, students and consultants whose career includes use or management of Electronic Design Automation (EDA) tools in modern digital and analog design.
There is lot of information going around on opportunities in VLSI in India. My best wishes to Shrivatsan, and hope that India gets a great VLSI engineer.
Lastly, I would like to invite knowledgeable people to send me links, etc. on any good sites, education institutes in India, pertaining to VLSI. I will publish the links and information on my blog and also acknowledge those people. Many thanks!
Thursday, March 6, 2008
Using 'semicon' simulation for drug discovery
Most of us have heard of simulation in semiconductors. However, using the technique in drug discovery/pharmaceuticals is indeed unique. The Cellworks Group Inc. (CWG) has managed to achieve this unique status by developing in silico based physiologically aligned predictive analysis platforms based on a systems biology approach.
These contain quantitative and dynamic maps of metabolic and cell signaling pathways, which are relevant to several diseases like cancer, inflammation, diabetes, CNS, infectious diseases, etc. The company was founded in June 2005, with corporate office in California, USA and the R&D team stationed in Bangalore, India.
Taher Abbasi, CEO & COO, CWG and Cellworks Research India Pvt Ltd, said that drug researchers can "simulate" these in silico platforms with various disease triggers, biological target inhibition/activation to represent functional drug action, patient sub-types with the overall objective to understand the disease physiology and treatment therapies in the context of a physiological view.
Simulation in pharma
Modeling and simulation have been used very successfully in fields such as aeronautics and semiconductors. However, their adaptability within the pharmaceutical domain has been anemic until now. Physiology simulation and modeling is crucial for identifying the issues early in the development cycle and in creating more efficacious and safer drugs.
Abbasi, a former Cadence employee, said: "Coming from the VLSI/chip industry, we are used to using automation technologies, especially simulation. One of our co-founders is Dr. Shireen Vali, who has a deep scientific background. We looked at how we could bring in the concept of simulation into drug discovery." The company has just crossed 65 members and is growing. "We have covered a pretty broad range of diseases and we have also brought together people who are experts in their respective fields."
Cellworks took the idea of simulation into drug discovery by looking at diseases, identifying the biological processes involved with a particular disease, and then looking at the biological players -- such as proteins, enzymes, etc., finally leading to building a unique dynamic map -- which is underlined by mathematics, he added. "As it is mathematics, it is similar to say, looking at transistors," he said.
Cellworks has an underlying computational engine, which is an OD (ordinary differential equations) solver, and solves those. The first layer is biology, the second -- mathematics, and the third -- semiconductors. Abbasi said: "Under the hood, we have put in the best practices of the semiconductor industry, especially, the automation part. This should handle pathways, runtime capacity and analysis capability to probe the system for data."
Cellworks' goal is crystal clear. Its mission is to be the infrastructure supplier to the pharmaceutical industry, by enabling the different components of this industry to carry out drug discovery. Besides this, Cellworks also aims to become the equivalent of Goggle Maps/Earth for understanding the human physiology, disease progression and predict the biological responses and therapeutic effects of drugs.
Huge market opportunity
So what is the market opportunity in this domain? As per Cellworks' estimate, the total available market (TAM) is said to be worth $1bn+ for collaborative R&D, disease platforms and in-house drug research. The pharmaceuticals and biotech industries spend over $51bn yearly on drug research.
The vast majority of this money goes into projects that have to be cancelled because of unanticipated side-effects, toxicity or lack of potency which is discovered in clinicals when very large expenses have already been incurred. Abbasi added, "We will and we can create and own the largest and most comprehensive IP of the dynamic physiological maps and computational infrastructure for the in silico analysis of cell physiology and disease pathology."
He pointed out that the only way to reduce costs and improve on the first time succession is to prototype a drug in a virtual environment -- similar to simulation in semiconductors/chip design. "The key is to first get the biology right, followed by the focus on chemistry, which is similar to frontend and backend in chip design," he noted. "Only then can you drive the in vitro and in vivo experiments through in silico."
Cellworks has already tasted early success. So far, it has created seven base disease platforms, which are physiologically validated. It is also working on live projects with initial customers, collaborators on these platforms. These platforms contain 100+ validated sub-pathways, which model over 10,000 reactions and 30,000 parameters.
The seven base disease platforms include: oncology platform (Glioma, Breast cancer), inflammation platform (RA and IBD), metabolic-syndrome platform (Diabetes II), skin (Pigmentation), pre-term endocrinology, infectious diseases, and neuro-degenerative disease platform (Parkinson's).
Cellworks has established strong active collaborations/partnerships in several areas. Notable being the UC Davis relationship in oncology, neuro-science, pharmacokinetics and inflammation; Cedar-Sinai/UCLA on pediatrics/pre-term delivery research, NIMHANS in Bangalore, for CNS work; UoH for oncology and Indian Institute of Sciences, Bangalore for heat shock proteins.
Cellworks has created a fast and scalable software platform for validation and analysis of disease platforms. The software platform allows it to simulate and verify at the subsystem level as well as at the disease level. It enables easy integration and re-use of models, intuitive debug and analysis of the platform. Next, it has a natural language processing system for enabling pathway analysis and validation.
Abassi added: "We are working with Orchid Chemicals on an arthritis project. We had real success regarding the usage of our technology in various R&D and production projects." Most of the R&D is done out of India, with only two people based in the US for marketing/sales.
Cellworks had done a small round of funding in January 2007 worth $1mn. Abbasi said, "We will do another round of funding in Q3-08 now that we have success stories and customers in place."
These contain quantitative and dynamic maps of metabolic and cell signaling pathways, which are relevant to several diseases like cancer, inflammation, diabetes, CNS, infectious diseases, etc. The company was founded in June 2005, with corporate office in California, USA and the R&D team stationed in Bangalore, India.
Taher Abbasi, CEO & COO, CWG and Cellworks Research India Pvt Ltd, said that drug researchers can "simulate" these in silico platforms with various disease triggers, biological target inhibition/activation to represent functional drug action, patient sub-types with the overall objective to understand the disease physiology and treatment therapies in the context of a physiological view.
Simulation in pharma
Modeling and simulation have been used very successfully in fields such as aeronautics and semiconductors. However, their adaptability within the pharmaceutical domain has been anemic until now. Physiology simulation and modeling is crucial for identifying the issues early in the development cycle and in creating more efficacious and safer drugs.
Abbasi, a former Cadence employee, said: "Coming from the VLSI/chip industry, we are used to using automation technologies, especially simulation. One of our co-founders is Dr. Shireen Vali, who has a deep scientific background. We looked at how we could bring in the concept of simulation into drug discovery." The company has just crossed 65 members and is growing. "We have covered a pretty broad range of diseases and we have also brought together people who are experts in their respective fields."
Cellworks took the idea of simulation into drug discovery by looking at diseases, identifying the biological processes involved with a particular disease, and then looking at the biological players -- such as proteins, enzymes, etc., finally leading to building a unique dynamic map -- which is underlined by mathematics, he added. "As it is mathematics, it is similar to say, looking at transistors," he said.
Cellworks has an underlying computational engine, which is an OD (ordinary differential equations) solver, and solves those. The first layer is biology, the second -- mathematics, and the third -- semiconductors. Abbasi said: "Under the hood, we have put in the best practices of the semiconductor industry, especially, the automation part. This should handle pathways, runtime capacity and analysis capability to probe the system for data."
Cellworks' goal is crystal clear. Its mission is to be the infrastructure supplier to the pharmaceutical industry, by enabling the different components of this industry to carry out drug discovery. Besides this, Cellworks also aims to become the equivalent of Goggle Maps/Earth for understanding the human physiology, disease progression and predict the biological responses and therapeutic effects of drugs.
Huge market opportunity
So what is the market opportunity in this domain? As per Cellworks' estimate, the total available market (TAM) is said to be worth $1bn+ for collaborative R&D, disease platforms and in-house drug research. The pharmaceuticals and biotech industries spend over $51bn yearly on drug research.
The vast majority of this money goes into projects that have to be cancelled because of unanticipated side-effects, toxicity or lack of potency which is discovered in clinicals when very large expenses have already been incurred. Abbasi added, "We will and we can create and own the largest and most comprehensive IP of the dynamic physiological maps and computational infrastructure for the in silico analysis of cell physiology and disease pathology."
He pointed out that the only way to reduce costs and improve on the first time succession is to prototype a drug in a virtual environment -- similar to simulation in semiconductors/chip design. "The key is to first get the biology right, followed by the focus on chemistry, which is similar to frontend and backend in chip design," he noted. "Only then can you drive the in vitro and in vivo experiments through in silico."
Cellworks has already tasted early success. So far, it has created seven base disease platforms, which are physiologically validated. It is also working on live projects with initial customers, collaborators on these platforms. These platforms contain 100+ validated sub-pathways, which model over 10,000 reactions and 30,000 parameters.
The seven base disease platforms include: oncology platform (Glioma, Breast cancer), inflammation platform (RA and IBD), metabolic-syndrome platform (Diabetes II), skin (Pigmentation), pre-term endocrinology, infectious diseases, and neuro-degenerative disease platform (Parkinson's).
Cellworks has established strong active collaborations/partnerships in several areas. Notable being the UC Davis relationship in oncology, neuro-science, pharmacokinetics and inflammation; Cedar-Sinai/UCLA on pediatrics/pre-term delivery research, NIMHANS in Bangalore, for CNS work; UoH for oncology and Indian Institute of Sciences, Bangalore for heat shock proteins.
Cellworks has created a fast and scalable software platform for validation and analysis of disease platforms. The software platform allows it to simulate and verify at the subsystem level as well as at the disease level. It enables easy integration and re-use of models, intuitive debug and analysis of the platform. Next, it has a natural language processing system for enabling pathway analysis and validation.
Abassi added: "We are working with Orchid Chemicals on an arthritis project. We had real success regarding the usage of our technology in various R&D and production projects." Most of the R&D is done out of India, with only two people based in the US for marketing/sales.
Cellworks had done a small round of funding in January 2007 worth $1mn. Abbasi said, "We will do another round of funding in Q3-08 now that we have success stories and customers in place."
Tuesday, January 29, 2008
R&D innovation: nano-scale to tera-scale
Justin Rattner, VP and Senior Fellow CTO, Intel Corp., while speaking at the recently held CXO Forum organized by the India Semiconductor Association (ISA), highlighted the various innovations Intel has created over the years and continues to do so.There are some hurdles to innovation. For instance, success brings conservatism and then, there is the curse of high-volume manufacturing. It led to Andy Grove's famous statement: "Only the paranoid survive". Obviously, massive inertia and innovation do not blend. Rattner mentioned certain external hurdles, especially, anti-Innovation policies and standards that hamper innovation.
Moore's Law drives innovation
Moore’s Law has been driving innovation at Intel. These have been in the form of high-K metal gate transistors at 45nm -- the first new transistor architecture in 35 years! There's more, in form of phase change memory (PCM) below 45nm, non-planar tri-gate transistor beyond 32nm, and carbon nanotube transistor
Some recent multi-disciplinary innovations include 45nm Core 2 Duo, Nehalem uArch, power management, quad core through package technology, Silverthorne/LPIA, USB/PCI Express, vPro, and WiMAX and 802.11n, respectively. Intel has made sustained Advances in silicon technology. In 2007, it developed 32nm SRAM with 1.9 billion transistors, with 32nm slated for 2009.
Sustained advances in micro-architecture include Intel Core -- new microarchitecture 65nm (2006), Penryn compaction/derivative at 45nm (2007), Nehalem -- new microarchitecture 45nm (2008), Westmere compaction/derivative 32nm (2009), and Sandy Bridge new microarchitecture 32nm (2010). "This shows our sustained microprocessor leadership," added Rattner.
There are plans to further reinvigorate Intel architecture -- by high throughput computing, IA programmability, ease of scaling for software, array of enhanced IA cores, and increasing teraflops of performance. Its 45nm Silverthorne is based on the Menlow platform and promises 'Full Internet in Your Pocket.'
Intel has also made advances in integration and packaging, such as multi chip packages, Wifi + WiMAX, processor + chipsets + accelerators, 60 percent smaller CPU packages, and 100 percent lead-free technology*. By 2008, Intel is committed to having all 45nm CPUs halogen free.
Innovations in memory, communications
Intel has also made innovations in memory technology. Robson Technology, which has NAND Flash cache, has 1.5X faster application load times, has 1.5X resume from hibernate, gives 0.4W average power savings, and is used in the Santa Rosa platform.
The other innovation is solid-state drives. These are embedded in a range of devices, from handhelds to servers. Compared to HDDs, these give 1/10th the power, >10X performance, and are 1,000X more durable.
Innovations in communication technology include things like adaptive antenna and front-ends, digital CMOS radio, and reconfigurable baseband. Intel has also developed the world’s 1st TeraFLOPS supercomputer on a die. It features 80 cores, 1TFLOP at 62W, and 256 GB/s bisection.
Intel has also unleashed the era of tera. These are in the form of tera bits –- Si Photonics and tera bytes –- 3D stacked memory. The latter includes 256KB SRAM per core, 4X C4 bump density, and 3200 thru-silicon vias.
Similarly, Intel's innovation in tera-scale software include RMS workloads, C++ for parallelism, Ct for nested data parallelism (race-free irregular parallel computation), and hardware assisted STM C transactional memory, which ensures concurrent access with no errors.
Intel has also done innovations for emerging regions. Rattner touched upon Research (at the Berkeley Lablet), which involves a long-distance WiFi solution: 6Mb/s at 100+ km. This has been tested at the Aravind Eye Hospital in Tamil Nadu. It has allowed doctor/patient videoconferences. Thirteen rural villages have been connected so far, going on to 50 villages. The impact has been tremendous -- 2,500 exams per month, over 30,000 so far; cataracts, glaucoma, cornea problems have been diagnosed; and 3,000 people have had their vision restored so far.
Intel has also been a champion in innovating through collaboration. These have been in form of academic open-collaborative (pre-competitive research) -- Carnegie Mellon, Berkeley, University of Washington; industrial partnerships (product differentiation) -- an example being the ciscointelalliance.com, and consortium (ecosystem benefit) -- via the ISA, Continua, Innovation Value Institute, Trusted Computing Group, etc.
Intel's focus areas for 2008 include:
a) tera-scale computing -- unleashing the next generation of applications.
b) Platform* on a chip (POC) -- 'Platform' integration on chip with IA.
c) Trusted services -- technologies for secure service opportunities.
d) Carry small, live large -- context aware usage models and platforms.
e) Ultimate connectivity -- connected 'all-ways' for future platforms.
Wednesday, January 23, 2008
LabVIEW 8.5 delivers power of multicore processors
National Instruments (NI) recently released the latest version of LabVIEW -- LabVIEW 8.5, which delivers the power of multi-core processors to engineers and scientists.
According to Jayaram Pillai, MD, India, Russia & Arabia, NI, new processors with multicore are coming out. Processing power is now split into two separate cores. With multicore, you are doing parallel processing. LabVIEW is a very dataflow programming tool. It is not sequential -- it is decided by the data itself. And inherently, it has always been parallel processing. NI has taken the advantage from LabVIEW 5 -- due to dual-core processing. It used multi-threaded architecture.
Assign different tasks on different cores
With processor technology shifting to multi-core, there is a need to run efficiently on the processor. For LabVIEW, you can assign different tasks on different cores -- which are independent. They don't have to run at the same speed. Those are the challenges multi-core seeks to address.
The technology NI has, the single application that you can build in LabVIEW, it aids in taking advantage of multicore. Part of a program can be assigned to one core. Another part is, if you don't want to club, it can run on the another core. All of this happens on one program.
So how is the new version better? As you want to accomplish more things, you have to go to higher levels of extractions (or abstractions). The graphical program is a very high level of abstraction. You can accomplish more with the graphical programming.
Another area where LabVIEW is finding itself is in the design space. Building systems today is very complex. NI builds into three stages -- design-prototype-deploy.
As an example, the Railways want to detect trains that have bad wheels. They collect data from railway lines -- lot of signal processing and maths were done. NI knows how to detect defective wheels. It put sensors to that signal, go to the field and do some trials. Once you know the algorithms and the BIOS required, you can go into designing. You take the prototype and make that into a product. Each stage, in the past, used different tools.
Since it is all the way -- from design to deployment -- it can all be done with LabVIEW. This capability -- that it can start at design and prototype, etc., brings greater value to engineers. NI call this process as graphical system design.
Community LabVIEW
Commenting on NI's activities in India, Jayaram Pillai said LabVIEW 8.5 is a major release. "Over the last 10 years we've been in India, we have changed its hardware platdform. One thing that remains common is LabVIEW and what it does for scientists and engineers. We've been able to create a community around LabVIEW. There are users and programmers of LabVIEW. There are certified developers, companies that have been built around LabVIEW. There are applications built around LabVIEW," he added.
Looking at graphical programming, over the last 10 yrs -- the biggest challenge for Pillai has been to address customers needs for engineers who can program LabVIEW. There's enough excitement in the market about LabVIEW. There are 1,100 jobs at least for LabVIEW.
There are people writing toolkits that can work with LabVIEW, which includes IP, developers, companies, customers, products, systems built around LabView. This has been happening within India.
Pillai said that similar to any technology adoption, there's a take-off stage. "It is called the S Curve, and we are at the bottom of the curve. The potential is huge. Our big challenge is to be able to create more engineers in the market. I feel that over 1,000 engineers are required," he added.
From an academic standpoint -- India has about 400,000+ engineers passing out each year. Only 25 percent are hireable, with reasonable training, by companies. The IITs, state governments, etc. take care of it. That means, there are business opportunities for companies to start finishing schools for training these people for the industry.
Lots of companies are getting into these finishing schools. These students will learn about the tools that they would later need to use.
Pillai stressed that it was important how the country looks at academicians. He said: "We haven't got into this stage as much. The IT industry has done very well and created a huge appetite for engineers. The majority of engineers passing out are hired by the IT companies."
He added: "LabVIEW is getting accepted by people in various projects. We've created a LabVIEW community -- the whole ecosystem."
Outlook for 2008
According to Pillai, algorithm enineering is key during the design phase. LabVIEW 8.5 has a new tool for design stage of the graphical system design.
With LabVIEW, users can increase performance through graphical programming for multi-core processors and FPGAs. Pillai said: "At the design stage, you want to give the engineer multiple computing options. The engineer is concerned about deployment, but he would like to move from Windows to real-time. This should be done seamlessly. LabVIEW FPGA has been around for a long time."
Programming in FPGA is not simple. NI's offer to engineers is: look at the FPGA as a platform and program it freely without even needing to know what's the VHDL code! LabVIEW can run on Windows, and move to RTOS and FPGA, and all of it is seamless.
As an example, Lego has a product called Mindstorm -- a robot. That robot has sensors. It is targeted at 10-yr olds. On one side, a 10-yr old can program LabVIEW. All details are there in LabVIEW. On another side, it can be used in the largest, physics experiments. So LabVIEW is not complex to use.
LabView has been shipping formally since last month.
According to Jayaram Pillai, MD, India, Russia & Arabia, NI, new processors with multicore are coming out. Processing power is now split into two separate cores. With multicore, you are doing parallel processing. LabVIEW is a very dataflow programming tool. It is not sequential -- it is decided by the data itself. And inherently, it has always been parallel processing. NI has taken the advantage from LabVIEW 5 -- due to dual-core processing. It used multi-threaded architecture.
Assign different tasks on different cores
With processor technology shifting to multi-core, there is a need to run efficiently on the processor. For LabVIEW, you can assign different tasks on different cores -- which are independent. They don't have to run at the same speed. Those are the challenges multi-core seeks to address.
The technology NI has, the single application that you can build in LabVIEW, it aids in taking advantage of multicore. Part of a program can be assigned to one core. Another part is, if you don't want to club, it can run on the another core. All of this happens on one program.
So how is the new version better? As you want to accomplish more things, you have to go to higher levels of extractions (or abstractions). The graphical program is a very high level of abstraction. You can accomplish more with the graphical programming.
Another area where LabVIEW is finding itself is in the design space. Building systems today is very complex. NI builds into three stages -- design-prototype-deploy.
As an example, the Railways want to detect trains that have bad wheels. They collect data from railway lines -- lot of signal processing and maths were done. NI knows how to detect defective wheels. It put sensors to that signal, go to the field and do some trials. Once you know the algorithms and the BIOS required, you can go into designing. You take the prototype and make that into a product. Each stage, in the past, used different tools.
Since it is all the way -- from design to deployment -- it can all be done with LabVIEW. This capability -- that it can start at design and prototype, etc., brings greater value to engineers. NI call this process as graphical system design.
Community LabVIEW
Commenting on NI's activities in India, Jayaram Pillai said LabVIEW 8.5 is a major release. "Over the last 10 years we've been in India, we have changed its hardware platdform. One thing that remains common is LabVIEW and what it does for scientists and engineers. We've been able to create a community around LabVIEW. There are users and programmers of LabVIEW. There are certified developers, companies that have been built around LabVIEW. There are applications built around LabVIEW," he added.
Looking at graphical programming, over the last 10 yrs -- the biggest challenge for Pillai has been to address customers needs for engineers who can program LabVIEW. There's enough excitement in the market about LabVIEW. There are 1,100 jobs at least for LabVIEW.
There are people writing toolkits that can work with LabVIEW, which includes IP, developers, companies, customers, products, systems built around LabView. This has been happening within India.
Pillai said that similar to any technology adoption, there's a take-off stage. "It is called the S Curve, and we are at the bottom of the curve. The potential is huge. Our big challenge is to be able to create more engineers in the market. I feel that over 1,000 engineers are required," he added.
From an academic standpoint -- India has about 400,000+ engineers passing out each year. Only 25 percent are hireable, with reasonable training, by companies. The IITs, state governments, etc. take care of it. That means, there are business opportunities for companies to start finishing schools for training these people for the industry.
Lots of companies are getting into these finishing schools. These students will learn about the tools that they would later need to use.
Pillai stressed that it was important how the country looks at academicians. He said: "We haven't got into this stage as much. The IT industry has done very well and created a huge appetite for engineers. The majority of engineers passing out are hired by the IT companies."
He added: "LabVIEW is getting accepted by people in various projects. We've created a LabVIEW community -- the whole ecosystem."
Outlook for 2008
According to Pillai, algorithm enineering is key during the design phase. LabVIEW 8.5 has a new tool for design stage of the graphical system design.
With LabVIEW, users can increase performance through graphical programming for multi-core processors and FPGAs. Pillai said: "At the design stage, you want to give the engineer multiple computing options. The engineer is concerned about deployment, but he would like to move from Windows to real-time. This should be done seamlessly. LabVIEW FPGA has been around for a long time."
Programming in FPGA is not simple. NI's offer to engineers is: look at the FPGA as a platform and program it freely without even needing to know what's the VHDL code! LabVIEW can run on Windows, and move to RTOS and FPGA, and all of it is seamless.
As an example, Lego has a product called Mindstorm -- a robot. That robot has sensors. It is targeted at 10-yr olds. On one side, a 10-yr old can program LabVIEW. All details are there in LabVIEW. On another side, it can be used in the largest, physics experiments. So LabVIEW is not complex to use.
LabView has been shipping formally since last month.
Monday, January 14, 2008
Power awareness critical for chip designers
The holy grail of electronics -- low-power design, or having the requisite power awareness is extremely critical for chip designers working on both high-performance applications and portable applications. For one, it determines the battery lifetime of a device, besides determining the cooling and energy costs. It is said that several of today's chip designs are limited in terms of power and still require maximum performance.
Touching on the global factors, S.N. Padmanabhan, Senior Vice President, Mindtree Consulting, said the Kyoto Protocol mandates energy conservation efforts.
Low-power design challenges
Asia, as we all know, has been emerging as a major energy consuming society. Shortage of electricity is becoming a major concern. There is a huge strain on nations to meet the rising needs/halt rise. There is also a rapid increase in all types of electronic goods in growing economies. As a result, increased efficiencies and reduced consumption should be beneficial as a whole!
In the Indian context, the country has around 125 million televisions sets, 5 million automatic washing machines, 10 million white goods, 200+ million other electronics, over 90 million cell phones and 50 million land lines, etc. A 1W reduction in white goods and TVs would lead to a saving of 140 Mi Watts of power! And, a 10 mW reduction in phones will save 1.4 Mi Watts!! Therefore, it makes even more sense to go low power!
Mindtree's Padmanabhan said IC power budgets have come down drastically. It is <2W for four out of five chips designed. There has also been a simultaneous manipulation of multiple parameters (P=CV2f). Next, there are several leakage issues in 65nm and smaller geometries, which can no longer be ignored.
Add to all of these are factors that there is a lack of availability of comprehensive tools and techniques, as well as analog designs. In such a scenario, designers need to be very clear about their objectives -- is it achieving lowering average power, lowering the maximum peak power or lowering energy.
Jayanta Kumar Lahiri, Director, ARM, pointed out challenges associated with batteries. Battery storage has been a limiting factor. Battery energy doubles in a decade and surely, does not follow the Moore’s law. Next, there have hardly been major changes in the basic battery technology. The energy density/size safe handling are limiting factors as well for batteries.
He added that the low-power challenge is four-fold in the VLSI domain. These are -- leakiness; more integration means more W/cm^2; EDA tools not that good in low power domain and does not co-relate sometimes with the silicon, and variability of device parameters make things worse.
Toshiyuki Saito, Senior Manager, Design Engineering Division NEC Electronics Japan, said low power is necessary for customer's success -- in form of heat suppress for wired systems and improved battery life time for mobile systems. It also brings cost competitiveness for SoC suppliers in terms of packaging cost, and development cost and turnaround time. Finally, it would contribute to preserving the global environment.
Addressing low power challenges
What are semiconductor and EDA companies doing to address the low-power design challenges? Padmanabhan said several techniques were being employed at the circuit level. However, each one of those had limitations.
These include AVS -- which provides maximum savings, reduces speed, but may need compensation; clock gating -- which does not help to reduce leakage and needs additional gates; and adaptive clock scaling -- which needs sophistication and is not very simple; and finally, the use of multi threshold cells for selective trade-off.
Emerging techniques include efficient RTL synthesis techniques, which is fast, but leaky, vs. slow and low power; power aware resource sharing, which is planning to be done at the architectural level and synthesis, but is not as widely used as other techniques; and power gating methodology -- which makes use of sleep transistors, has coarse and fine grained methods, reduces dynamic and leakage power, and also exploits idle times of the circuit.
He added that power optimization should start at the architecture and design stages. Maximum optimization can be achieved at the system level. Also, the evolving power optimization tools and methodologies required collaborative approaches.
Power Forward Initiative
Pankaj Mayor, Group Director, Industry Alliances, Cadence Design Systems, said low power imperative is driving the semiconductor and EDA industries. He said, "design-based low power solution is the only answer!" Traditional design-based solutions are fragmented. Basic low power design techniques, such as area optimization, multi-Vt optimization and clock gating were automated in the 1990s.
There has since been an impact of advanced low-power techniques. These advanced techniques include multi-supply voltage (MSV), power shut-off (PSO), dynamic and adaptive voltage frequency scaling (DVFS and AVS), and substrate biasing. Cadence's low-power solution uses advanced techniques.
According to Mayor, the Power Forward Initiative (PFI) has created an ecosystem as well. The Power Forward Initiative includes Cadence and 23 other companies across the design chain, as of the end of December 2007.
The year 2007 also saw a continued Power Forward industry momentum. In Q1-07, Common Power Format or CPF became the Si2 [Silicon Integration Initiative] standard. The Cadence Low Power Solution production released V 1.0 in this quarter as well. In H2-07, the industry has seen over 100 customers adopting CPF-based advanced low power solution as well as ~50 tapeouts.
CPF allows holistic automation and validation at every design step. Arijit Dutta, Manager, Design Methodology, Freescale Semiconductor exhibited the advantages of using the CPF in wireless, networking and automotive verticals at Freescale.
Touching on the global factors, S.N. Padmanabhan, Senior Vice President, Mindtree Consulting, said the Kyoto Protocol mandates energy conservation efforts.
Low-power design challenges
Asia, as we all know, has been emerging as a major energy consuming society. Shortage of electricity is becoming a major concern. There is a huge strain on nations to meet the rising needs/halt rise. There is also a rapid increase in all types of electronic goods in growing economies. As a result, increased efficiencies and reduced consumption should be beneficial as a whole!
In the Indian context, the country has around 125 million televisions sets, 5 million automatic washing machines, 10 million white goods, 200+ million other electronics, over 90 million cell phones and 50 million land lines, etc. A 1W reduction in white goods and TVs would lead to a saving of 140 Mi Watts of power! And, a 10 mW reduction in phones will save 1.4 Mi Watts!! Therefore, it makes even more sense to go low power!
Mindtree's Padmanabhan said IC power budgets have come down drastically. It is <2W for four out of five chips designed. There has also been a simultaneous manipulation of multiple parameters (P=CV2f). Next, there are several leakage issues in 65nm and smaller geometries, which can no longer be ignored.
Add to all of these are factors that there is a lack of availability of comprehensive tools and techniques, as well as analog designs. In such a scenario, designers need to be very clear about their objectives -- is it achieving lowering average power, lowering the maximum peak power or lowering energy.
Jayanta Kumar Lahiri, Director, ARM, pointed out challenges associated with batteries. Battery storage has been a limiting factor. Battery energy doubles in a decade and surely, does not follow the Moore’s law. Next, there have hardly been major changes in the basic battery technology. The energy density/size safe handling are limiting factors as well for batteries.
He added that the low-power challenge is four-fold in the VLSI domain. These are -- leakiness; more integration means more W/cm^2; EDA tools not that good in low power domain and does not co-relate sometimes with the silicon, and variability of device parameters make things worse.
Toshiyuki Saito, Senior Manager, Design Engineering Division NEC Electronics Japan, said low power is necessary for customer's success -- in form of heat suppress for wired systems and improved battery life time for mobile systems. It also brings cost competitiveness for SoC suppliers in terms of packaging cost, and development cost and turnaround time. Finally, it would contribute to preserving the global environment.
Addressing low power challenges
What are semiconductor and EDA companies doing to address the low-power design challenges? Padmanabhan said several techniques were being employed at the circuit level. However, each one of those had limitations.
These include AVS -- which provides maximum savings, reduces speed, but may need compensation; clock gating -- which does not help to reduce leakage and needs additional gates; and adaptive clock scaling -- which needs sophistication and is not very simple; and finally, the use of multi threshold cells for selective trade-off.
Emerging techniques include efficient RTL synthesis techniques, which is fast, but leaky, vs. slow and low power; power aware resource sharing, which is planning to be done at the architectural level and synthesis, but is not as widely used as other techniques; and power gating methodology -- which makes use of sleep transistors, has coarse and fine grained methods, reduces dynamic and leakage power, and also exploits idle times of the circuit.
He added that power optimization should start at the architecture and design stages. Maximum optimization can be achieved at the system level. Also, the evolving power optimization tools and methodologies required collaborative approaches.
Power Forward Initiative
Pankaj Mayor, Group Director, Industry Alliances, Cadence Design Systems, said low power imperative is driving the semiconductor and EDA industries. He said, "design-based low power solution is the only answer!" Traditional design-based solutions are fragmented. Basic low power design techniques, such as area optimization, multi-Vt optimization and clock gating were automated in the 1990s.
There has since been an impact of advanced low-power techniques. These advanced techniques include multi-supply voltage (MSV), power shut-off (PSO), dynamic and adaptive voltage frequency scaling (DVFS and AVS), and substrate biasing. Cadence's low-power solution uses advanced techniques.
According to Mayor, the Power Forward Initiative (PFI) has created an ecosystem as well. The Power Forward Initiative includes Cadence and 23 other companies across the design chain, as of the end of December 2007.
The year 2007 also saw a continued Power Forward industry momentum. In Q1-07, Common Power Format or CPF became the Si2 [Silicon Integration Initiative] standard. The Cadence Low Power Solution production released V 1.0 in this quarter as well. In H2-07, the industry has seen over 100 customers adopting CPF-based advanced low power solution as well as ~50 tapeouts.
CPF allows holistic automation and validation at every design step. Arijit Dutta, Manager, Design Methodology, Freescale Semiconductor exhibited the advantages of using the CPF in wireless, networking and automotive verticals at Freescale.
Indian designers could lead in EDA product development
There will be the multi-nationalization of the product development process, according to Walden C. Rhines, chairman & CEO, Mentor Graphics. More executives recognize that "access to qualified personnel" is the key driver. As per A.T. Kearney Global Services Location Index 2007, India is the most attractive offshoring destination. He was speaking at the Though Leadership Forum organized by the India Semiconductor Association.Touching on the evolution of EDA, and the role of Indian designers, Rhines said that most electronic engineers did not consider themselves "risk takers". Most electronic engineers also don't like to change tools and fewer even consider "hot" new tools.
On the contrary, young engineers and recent university graduates eagerly adopted new technology. It is a way for them to distinguish themselves, get the productivity advantage and they were less invested in existing methodologies.
Indian designers smart
Comparing Indian designers with the rest of the world, he said that electronic designers in India, on an average, are less experienced than in the United States, Europe and Japan. However, they are on an average, as smart, or smarter, than those in United States, Europe and Japan. There has been an increasing influence of India design centers on the multinational design flows and tools.
Disruptive change creates leadership opportunities. There has been improved power and cost through improved system architecture. The C synthesis enables faster architectural exploration and shorter time to Verilog.
C synthesis matches or exceeds hand coded RTL efficiency, as per STMicroelectronics (Reed-Solomon, Galois Field Multiplier). There have also been system architectural innovations to reduce die size -- Ericsson mobile platforms. There is a need to iterate to find the optimum architecture.
Now, Indian designers have been early adopters of C-based design. The reasons were, one there was a willingness to try new approaches and two, it caused multinational parent companies to accelerate their own adoption.
India is likely to be a leader in transaction level design. They have been able to extract fast, accurate power and timing models from RTL. They have managed runs 100x-1000x faster vs. RTL, retained accuracy at the gate level and RTL, their models run with application software for hardware/software cosimulation, and they have done transaction-based verification using emulation. It has been the same for UPF-compatible verification.
Some other areas of verification where India may lead the way are assertions, coverage based verification, and algorithmic test bench synthesis.
Adoption of place and route technology
Let us see how the adoption of new place and route technology has influenced the industry. When a design flow breaks, what breaks the most often? Place and route breaks every two technology generations. Technology generations ramp to peak volume. Place and route utilizes a semiconductor company's internal software until gate array routers emerge.
Cell-based layout requires hierarchical router with timing. Tangent attacks leading-edge 0.75 micron designs. Later, Cadence became the dominant place and route supplier at 0.35 micron as the fabless industry grew demand. [Cadence acquired Tangent in 1989]. However, at 0.25 microns, SoC drives new technology requirements. This led to the collapse of the FAM business model.
SoC needs "break" the flow. ArcSys emerged at 0.35/0.25 micron. It addresses SoC requirements for large sizes and interconnect delay. It goes public as Avant!, and is later acquired by Synopsys. However, a timing closure crisis emerges at 0.13 micron. Cadence and Avant!/Synopsys try to extend older tool architectures.
Now, timing closure "breaks" the design flow. At this point, Magma emerges at 0.13 micron with timing-driven layout solution. At 90nm, Magma dominates timing-driven design. It also approaches Cadence, Avant!/Synopsys place and route market share. What the industry witnesses is that a new problem emerges and a new, leading-edge solution provider enters every two nodes.
And now, pressures are creating 65/45nm discontinuity. These are process and design variations, low-power requirements, and large design data sizes. Explosive growth in complexity requires multi-corner, multi-mode analysis.
Achieving power/performance design goals requires analysis of corner cases for manufacturing and operational variability. Manufacturing variability multiplies the required corner cases. Hence, manufacturing variability now "breaks" the place and route flow at 65nm. With the advent of 45nm, it demands design for manufacturing (DFM), and ushers in more corners.
Implications for EDA in India
So what are the implications for EDA in this scenario, especially from an Indian context? One, introduce and support leading-edge design tools in India. Two, EDA startups will focus initial sales efforts in San Jose and India. Three, purchasing decisions will increasingly incorporate India design teams to drive flows and decisions. Four, India will emerge as the test bed for new design ideas. As a result, Indian designers would exercise their influence by demanding the best-in-class design tools and capabilities.
Indian designers should always remain open to new design approaches. They should beware of becoming risk adverse as they become more experienced. They should need to stay abreast of the emerging innovations by maintaining close contact with EDA companies, including start-ups. They also need to make EDA suppliers aware of their issues and challenges.
Tuesday, January 1, 2008
Can we expect exciting times in 2008?
Welcome 2008! May I wish all my readers a very happy and prosperous 2008. Another year's gone past. We have a habit of looking back to see at what happened and what could have been.
A lot has been written already about 2007 and what to expect in 2008. So let's just touch upon some of the events from 2007 and some expectations from 2008.
For India, 2007 was a great year for the semiconductor industry -- first, the Indian government announced the semiconductor policy, followed some months later by the fab policy. Both were tremendous firsts in India's science and technology, and not IT, history. Everyone hopes that the Indian semiconductor industry will take off this year. Eyes are focused on the embedded segment, what with the global semiconductor industry reportedly facing 'an embedded dilemma.'
An issue hitting the EDA industry is that, the cost of designing or developing the embededded software for an SoC actually passed the cost of desgining the SoC itself in 2007. The world needs to avoid this software crisis, and India is well placed to take full advantage and play a major role, given its strength in embedded.
In IT, it's been a mixed sort of a year for Apple, which hit big time with the iPhone, seemed not to make waves with either the Safari browser or the Leopard OS. Microsoft had the Vista OS, but then, Vista didn't exactly warm the hearts of users or those who wished to upgrade their OS, including yours truly. Maybe, 2008 would ring in better times for Vista.
While on browsers, Firefox has gained lot of ground. However, by the end of 2007 came the news that the Netscape Web browser -- which started it all -- would soon be confined to history.
Netscape Navigator was the world's first commercial Web browser and launch pad of the Internet boom. It will be taken off on February 1, 2008, after a 13-year run. Time Warner's AOL, its current owner, has reportedly decided to kill further development and technical support to focus on growing the company as an advertising business. The first version of Netscape had come out in late 1994.
In gaming, there are admirers of Wii, PS3 and Xbox 360, and will remain the same. Which one of these gaming consoles will reign supreme, eventually, is difficult to predict.
In consumer electronics, lines are surely blurring between portable media players (PMPs) and portable navigation devices. Also, it would be interesting to see how digital photo frames survive 2008. A reported tight supply, especially for seven-inch models, has led to some makers in Asia either postponing mass production or extending lead times. Surely, makers cannot add more entertainment functions in smaller screen models, to keep costs down.
In the security products market, IP cameras and video servers should have a better year, with more emphasis now on video surveillance. In fact, some friends have been querying me as well regarding their potential.
On components, we can hope to see more growth for solid polymer capacitors in 2008, and among PCBs some fabricators should start manufacturing high-density interconnect (HDI) PCBs this year.
In wireless, we should witness TD-SCDMA in operation prior to the Beijing Olympic Games. Backers would like to see TD-SCDMA succeed, given the effort Datang-Siemens has made on the technology, as also the Chinese government, which issued spectrum for TD-SCDMA nearly five years ago!
Let's all welcome 2008 and look forward to more exciting things happening.
A lot has been written already about 2007 and what to expect in 2008. So let's just touch upon some of the events from 2007 and some expectations from 2008.
For India, 2007 was a great year for the semiconductor industry -- first, the Indian government announced the semiconductor policy, followed some months later by the fab policy. Both were tremendous firsts in India's science and technology, and not IT, history. Everyone hopes that the Indian semiconductor industry will take off this year. Eyes are focused on the embedded segment, what with the global semiconductor industry reportedly facing 'an embedded dilemma.'
An issue hitting the EDA industry is that, the cost of designing or developing the embededded software for an SoC actually passed the cost of desgining the SoC itself in 2007. The world needs to avoid this software crisis, and India is well placed to take full advantage and play a major role, given its strength in embedded.
In IT, it's been a mixed sort of a year for Apple, which hit big time with the iPhone, seemed not to make waves with either the Safari browser or the Leopard OS. Microsoft had the Vista OS, but then, Vista didn't exactly warm the hearts of users or those who wished to upgrade their OS, including yours truly. Maybe, 2008 would ring in better times for Vista.
While on browsers, Firefox has gained lot of ground. However, by the end of 2007 came the news that the Netscape Web browser -- which started it all -- would soon be confined to history.
Netscape Navigator was the world's first commercial Web browser and launch pad of the Internet boom. It will be taken off on February 1, 2008, after a 13-year run. Time Warner's AOL, its current owner, has reportedly decided to kill further development and technical support to focus on growing the company as an advertising business. The first version of Netscape had come out in late 1994.
In gaming, there are admirers of Wii, PS3 and Xbox 360, and will remain the same. Which one of these gaming consoles will reign supreme, eventually, is difficult to predict.
In consumer electronics, lines are surely blurring between portable media players (PMPs) and portable navigation devices. Also, it would be interesting to see how digital photo frames survive 2008. A reported tight supply, especially for seven-inch models, has led to some makers in Asia either postponing mass production or extending lead times. Surely, makers cannot add more entertainment functions in smaller screen models, to keep costs down.
In the security products market, IP cameras and video servers should have a better year, with more emphasis now on video surveillance. In fact, some friends have been querying me as well regarding their potential.
On components, we can hope to see more growth for solid polymer capacitors in 2008, and among PCBs some fabricators should start manufacturing high-density interconnect (HDI) PCBs this year.
In wireless, we should witness TD-SCDMA in operation prior to the Beijing Olympic Games. Backers would like to see TD-SCDMA succeed, given the effort Datang-Siemens has made on the technology, as also the Chinese government, which issued spectrum for TD-SCDMA nearly five years ago!
Let's all welcome 2008 and look forward to more exciting things happening.
Monday, December 24, 2007
Semicon outlook 2008: Global market likely to grow 6-11 percent amid recession fears
While a majority of analysts at a recent panel discussion on global semiconductor outlook predicted semiconductor growth in the range of 6-11 percent during 2008, some other panelists predicted 2008 to be flat year or a year of negative growth.
There were fears of a possible recession in 2008, along with concerns surrounding consumer spend that could be hit by higher oil prices and the US mortgage crisis.
This panel discussion was organized last week by Semiconductor International, USA. Here is the full report.
Semi forecasts mixed for 2008
Amid concerns of a possible recession in the US economy in 2008, analysts at a recent Webcast hosted by Semiconductor International, were divided in their forecasts for the coming year. A majority predicted semiconductor growth to be in the range of 6-11 percent during 2008, while some others predicted 2008 to be flat year or a year of negative growth.
Anne Craib, director of Market Research, International Affairs and Finance, Semiconductor Industry Association (SIA), said the global economic situation needed to be factored in, as well as its impact on consumer demand.
She said: "Semiconductor demand is driven over 50 percent by consumer demand currently. That is something we should increasingly be aware of. Areas like gas prices and the home mortgage market are things that we previously would not have paid much attention to that we have had to take into account in our forecasting this cycle.” She was confident of the semiconductor industry reaching 7-8 percent CAGR during 2008.
Steve Szirom, President, InsideChips.com, added that many economists were predicting recession in 2008. He said: "The demand-supply balance should be somehwat better than this year. We may have a demand driven recession." He adopted a pessimistic view for 2008, predicting -8 percent growth.
DRAM weak, NAND bright
Gary Grandbois, principal analyst for iSuppli Corp., noted: “We have reduced our forecast to 7.5 percent for 2008 and think it might go lower than that. We think it’s going to be a negative first half. Certainly in the DRAM area, it’s looking very poor. We think it will improve in the second half, almost mirroring 2007, but giving us a far weaker year in 2008 than we’ve expected.”
Richard Gordon, Managing Vice President, Semiconductors, Gartner Dataquest Research, agreed with Grandbois, adding that DRAM would see a negative side in 2008. "Our forecast is 6 percent for 2008, and it doesn't factor in the US recession," he said.
While the DRAM market has been predicted to be negative next year, analysts see a positive market for NAND in 2008. New applications, such as WUSB (wireless USB), increase in cell phones, higher content in portable media players, etc., are likely to drive growth.
Commenting further on the outlook for 2008, Moshe Handelsman, President, Advanced Forecasting Inc., noted that 2007 would be the peak of current IC cycle. "From that point on, the underlying demand for semiconductors will decline and decline in 2008. We are negative about 2008," he added.
Carl Johnson, Executive Director, Research Infrastructure, concurred that the industry had become much more global. "We now have to look at the mortgage debacle, etc. Consumers will be very tight in first half of this year." He added, "I would say, next year's going to be flat."
Mike Cowan, an independent semiconductor industry analyst, said the growth would be about 8.15 percent during 2008. "The dynamics of the market and the industry will change month-to-month as well," he quipped.
Capex likely to dip in 2008
Regarding capex in 2008, Carl Johnson of Research Infrastructure, expects the next year to be bumpy as far as capital spending is concerned. "We're in a downturn right now. Foundries, who are investing lot more money in older process generations, and that is a function of some of the other older IDMs and fabs, are actually shutting down and saying, 'we can go over to the foundries and process wafers for less than what we can do it on our own'. We are seeing lot of consolidation within the fab space. Mid-level players are consolidating. The customer base is clearly narrowing."
The cost of designing some of these leading-edge devices, and getting them to market, and then following it up with another product, if you don't want to be a one-product guy, is a real challenge. That is limiting the number of players that are going into the mega fabs. So, the field is narrowing in 65nm, and 45nm, and as we get to below 45nm, the field is going to get much, much narrower.
According to him, capital spending is likely to be down in 2008. "I am predicting 10 percent down next year. There's also going to be a great consolidation in the devices manufacturing community, and also in the capital equipment community. We are seeing a number of M&A activities in the capital equipment business. It will also go into the supply chain business."
Gartner's Richard Gordon said the research firm was forecasting capex to be down by -15 percent in capex in 2008, and that includes -30 percent in the DRAM sector. He added: "Looking at the individual companies in the DRAM space, I won't be surprised to see that go even lower. So, -15 percent in capex can get even worse as 2008 unfolds. We will see it coming back. But, it will take a while for demand to catch up with supply."
EDA industry in catch-up mode
The EDA industry is said to be lagging behind the semiconductor industry at the moment, and is in the catch-up mode, according to Gary Smith, President, Gary Smith EDA.
Commenting on the outlook for the EDA market, Smith said the EDA industry is in a lttile unusual position. He said: "The market's been flat for the past four years. Tools for 65nm, 45nm silicon design have also been delayed." The R&D was not put in because of the recession. "Right now, we are in a position of lag in the market," he added.
EDA tools cover two process generations. The industry is just starting to introduce 65nm and 45nm tools. That generation is being called the DFM generation tool. Smith said: "It is even more important to the semiconductor industry as we run into manufacturing problems that they are relying on design tools to solve, rather than on semiconductor equipment." That's a major shift in the market!
EDA to grow 7.8 percent in 2008
According to him, the industry is now now into a pretty good growth area. "We were 11 percent last year, 10.2 percent to come in this year. We will be a bit down next year at 7.8 percent," he forecast. This has been attributed mainly to the EDA industry's lag in the market. "Some are moving to 32nm. And certainly, a lot of work is being done in 45nm," he added.
Smith noted: "The EDA industry is in the catch-up mode. We will lag them. We are expecting the downturn to really hit us in 2009. However, we are not an industry that goes negative often. No matter what you guys do, you still have to design something. So, when you go into recession, typically, the way you get out of recession is you generally design your way out!"
DFM, ESL growth drivers
Among the growth drivers is the DFM (design for manufacturing) issue, which is increasingly getting more complex. There is said to be a move to restrict the design rules that is in place now for 45nm. "We are going to see major changes in 32nm; that'll have impact on tools," he added.
The other issue is parallel computing that has become a major task for the EDA industry. "With signal threading, we can no longer handle designs over 100 million gates. Of course, at 45nm, you can do a 100mn gates. That rewriting process is another issue that is also slowing out down. That's a full three-year re-write," Smith said.
Further, EDA is also starting to move up into the ESL. The electronic-system level (ESL) is going to shift the EDA market more into the systems market, and serve less on its dependency on the semiconductor world.
New fabs in India, China
There have been a lot of announcements made regarding new fabs, especially in places such as India, China and Brazil.
Gary Grandbois at iSuppli said: "Brazil is a better example. India just announced that they are building new fabs. What we saw at the turn of the century is that the industry split into two areas -- one traditional components manufacturer and second is the SoC manufacturer. Those are the companies that need leading edge fabs."
According to him, the cost of R&D was going out of sight for process development. "We're also seeing consolidation of research groups. We expect that come down to five consortiums or less. All companies can afford do their own process development once the basic process has been developed."
There are going to be different types of fabs. With globalization, lot of countries may decide they want to have a fab. Brazil announced one. "You're going to see them all over the world. The market's going to change," he added.
Anne Craib from the Semiconductor Industry Association said: "If you look at the cost structure, it costs over $1bn to build and operate a fab in the US. The question is where is the fab going to be located? The US companies will continue to be major players. Again, the question is: where is it going to be economically feasible? The interest is outside of the US."
New elements likely in 32nm
On the subject of integration of MEMS, 3D, etc., Carl Johnson from Research Infrastructure said, "A very large topic with the design community is big change in computer architecture -- the big change is the multicore -- that's the biggest driver now."
Jim Feldhan, President, Semico Research Corp., noted that the industry is going to hit limits with silicon processing at some point of time. "We have to bring in new elements. In 32nm, there'll be only a handful of companies who can push real hard there and can afford it."
Push to 450mm fabs unlikely?
Finally, is there be going to be a push to 450mm fabs and how's the impact going to be like?
iSuppli's Gary Grandbois, said that curently the industry was expecting that it would need to abandon silicon in 2020. "If we don't have any silver bullets by then, we are going to use nano stuff to augment CMOS. We don't know what that's going to be."
He added: The issue is: are we going to use silicon at all in 2020? If we start developing equipment for 450mm, we're not going to have that very soon. What they have to consider, what is the payback for that move?"
We would love to hear from you on how you see the semiconductor industry going in 2008.
There were fears of a possible recession in 2008, along with concerns surrounding consumer spend that could be hit by higher oil prices and the US mortgage crisis.
This panel discussion was organized last week by Semiconductor International, USA. Here is the full report.
Semi forecasts mixed for 2008
Amid concerns of a possible recession in the US economy in 2008, analysts at a recent Webcast hosted by Semiconductor International, were divided in their forecasts for the coming year. A majority predicted semiconductor growth to be in the range of 6-11 percent during 2008, while some others predicted 2008 to be flat year or a year of negative growth.
Anne Craib, director of Market Research, International Affairs and Finance, Semiconductor Industry Association (SIA), said the global economic situation needed to be factored in, as well as its impact on consumer demand.
She said: "Semiconductor demand is driven over 50 percent by consumer demand currently. That is something we should increasingly be aware of. Areas like gas prices and the home mortgage market are things that we previously would not have paid much attention to that we have had to take into account in our forecasting this cycle.” She was confident of the semiconductor industry reaching 7-8 percent CAGR during 2008.
Steve Szirom, President, InsideChips.com, added that many economists were predicting recession in 2008. He said: "The demand-supply balance should be somehwat better than this year. We may have a demand driven recession." He adopted a pessimistic view for 2008, predicting -8 percent growth.
DRAM weak, NAND bright
Gary Grandbois, principal analyst for iSuppli Corp., noted: “We have reduced our forecast to 7.5 percent for 2008 and think it might go lower than that. We think it’s going to be a negative first half. Certainly in the DRAM area, it’s looking very poor. We think it will improve in the second half, almost mirroring 2007, but giving us a far weaker year in 2008 than we’ve expected.”
Richard Gordon, Managing Vice President, Semiconductors, Gartner Dataquest Research, agreed with Grandbois, adding that DRAM would see a negative side in 2008. "Our forecast is 6 percent for 2008, and it doesn't factor in the US recession," he said.
While the DRAM market has been predicted to be negative next year, analysts see a positive market for NAND in 2008. New applications, such as WUSB (wireless USB), increase in cell phones, higher content in portable media players, etc., are likely to drive growth.
Commenting further on the outlook for 2008, Moshe Handelsman, President, Advanced Forecasting Inc., noted that 2007 would be the peak of current IC cycle. "From that point on, the underlying demand for semiconductors will decline and decline in 2008. We are negative about 2008," he added.
Carl Johnson, Executive Director, Research Infrastructure, concurred that the industry had become much more global. "We now have to look at the mortgage debacle, etc. Consumers will be very tight in first half of this year." He added, "I would say, next year's going to be flat."
Mike Cowan, an independent semiconductor industry analyst, said the growth would be about 8.15 percent during 2008. "The dynamics of the market and the industry will change month-to-month as well," he quipped.
Capex likely to dip in 2008
Regarding capex in 2008, Carl Johnson of Research Infrastructure, expects the next year to be bumpy as far as capital spending is concerned. "We're in a downturn right now. Foundries, who are investing lot more money in older process generations, and that is a function of some of the other older IDMs and fabs, are actually shutting down and saying, 'we can go over to the foundries and process wafers for less than what we can do it on our own'. We are seeing lot of consolidation within the fab space. Mid-level players are consolidating. The customer base is clearly narrowing."
The cost of designing some of these leading-edge devices, and getting them to market, and then following it up with another product, if you don't want to be a one-product guy, is a real challenge. That is limiting the number of players that are going into the mega fabs. So, the field is narrowing in 65nm, and 45nm, and as we get to below 45nm, the field is going to get much, much narrower.
According to him, capital spending is likely to be down in 2008. "I am predicting 10 percent down next year. There's also going to be a great consolidation in the devices manufacturing community, and also in the capital equipment community. We are seeing a number of M&A activities in the capital equipment business. It will also go into the supply chain business."
Gartner's Richard Gordon said the research firm was forecasting capex to be down by -15 percent in capex in 2008, and that includes -30 percent in the DRAM sector. He added: "Looking at the individual companies in the DRAM space, I won't be surprised to see that go even lower. So, -15 percent in capex can get even worse as 2008 unfolds. We will see it coming back. But, it will take a while for demand to catch up with supply."
EDA industry in catch-up mode
The EDA industry is said to be lagging behind the semiconductor industry at the moment, and is in the catch-up mode, according to Gary Smith, President, Gary Smith EDA.
Commenting on the outlook for the EDA market, Smith said the EDA industry is in a lttile unusual position. He said: "The market's been flat for the past four years. Tools for 65nm, 45nm silicon design have also been delayed." The R&D was not put in because of the recession. "Right now, we are in a position of lag in the market," he added.
EDA tools cover two process generations. The industry is just starting to introduce 65nm and 45nm tools. That generation is being called the DFM generation tool. Smith said: "It is even more important to the semiconductor industry as we run into manufacturing problems that they are relying on design tools to solve, rather than on semiconductor equipment." That's a major shift in the market!
EDA to grow 7.8 percent in 2008
According to him, the industry is now now into a pretty good growth area. "We were 11 percent last year, 10.2 percent to come in this year. We will be a bit down next year at 7.8 percent," he forecast. This has been attributed mainly to the EDA industry's lag in the market. "Some are moving to 32nm. And certainly, a lot of work is being done in 45nm," he added.
Smith noted: "The EDA industry is in the catch-up mode. We will lag them. We are expecting the downturn to really hit us in 2009. However, we are not an industry that goes negative often. No matter what you guys do, you still have to design something. So, when you go into recession, typically, the way you get out of recession is you generally design your way out!"
DFM, ESL growth drivers
Among the growth drivers is the DFM (design for manufacturing) issue, which is increasingly getting more complex. There is said to be a move to restrict the design rules that is in place now for 45nm. "We are going to see major changes in 32nm; that'll have impact on tools," he added.
The other issue is parallel computing that has become a major task for the EDA industry. "With signal threading, we can no longer handle designs over 100 million gates. Of course, at 45nm, you can do a 100mn gates. That rewriting process is another issue that is also slowing out down. That's a full three-year re-write," Smith said.
Further, EDA is also starting to move up into the ESL. The electronic-system level (ESL) is going to shift the EDA market more into the systems market, and serve less on its dependency on the semiconductor world.
New fabs in India, China
There have been a lot of announcements made regarding new fabs, especially in places such as India, China and Brazil.
Gary Grandbois at iSuppli said: "Brazil is a better example. India just announced that they are building new fabs. What we saw at the turn of the century is that the industry split into two areas -- one traditional components manufacturer and second is the SoC manufacturer. Those are the companies that need leading edge fabs."
According to him, the cost of R&D was going out of sight for process development. "We're also seeing consolidation of research groups. We expect that come down to five consortiums or less. All companies can afford do their own process development once the basic process has been developed."
There are going to be different types of fabs. With globalization, lot of countries may decide they want to have a fab. Brazil announced one. "You're going to see them all over the world. The market's going to change," he added.
Anne Craib from the Semiconductor Industry Association said: "If you look at the cost structure, it costs over $1bn to build and operate a fab in the US. The question is where is the fab going to be located? The US companies will continue to be major players. Again, the question is: where is it going to be economically feasible? The interest is outside of the US."
New elements likely in 32nm
On the subject of integration of MEMS, 3D, etc., Carl Johnson from Research Infrastructure said, "A very large topic with the design community is big change in computer architecture -- the big change is the multicore -- that's the biggest driver now."
Jim Feldhan, President, Semico Research Corp., noted that the industry is going to hit limits with silicon processing at some point of time. "We have to bring in new elements. In 32nm, there'll be only a handful of companies who can push real hard there and can afford it."
Push to 450mm fabs unlikely?
Finally, is there be going to be a push to 450mm fabs and how's the impact going to be like?
iSuppli's Gary Grandbois, said that curently the industry was expecting that it would need to abandon silicon in 2020. "If we don't have any silver bullets by then, we are going to use nano stuff to augment CMOS. We don't know what that's going to be."
He added: The issue is: are we going to use silicon at all in 2020? If we start developing equipment for 450mm, we're not going to have that very soon. What they have to consider, what is the payback for that move?"
We would love to hear from you on how you see the semiconductor industry going in 2008.
Subscribe to:
Posts (Atom)
