Cadence announces broad portfolio of 3D memory verification IP

SAN JOSE, USA: Cadence Design Systems Inc. announced the immediate availability of verification IP (VIP) supporting all popular 3D memory standards including Wide I/O 2, Hybrid Memory Cube (HMC), High Bandwidth Memory (HBM) and DDR4 3D Stacking (DDR4-3DS).

The portfolio of memory VIP enables designers to accelerate the verification of memory interfaces and achieve earlier system-on-chip (SoC) verification closure for compute server applications, mobile devices, high-performance graphics and network applications.

Advanced features of these new VIP models include direct memory access for read, write, save, preload and comparison of memory contents, robust assertions, error configurability, transaction callbacks, assertion reports and a built-in address manager.

Additionally, the models support all leading third party simulators, verification languages and methodologies, enabling SoC verification teams with the fastest path to verify the correctness of interfaces to these new, specialized memories.

"Memory is a critical factor in increasing functionality and performance of advanced system topologies," said Robert Feurle, VP of compute and networking marketing at Micron. "The fact that Cadence is involved in the development of all the latest standards enables our designers to accelerate their adoption of innovative technologies such as Hybrid Memory Cube."

"3D memories are increasingly becoming essential to the next generation of electronic products," said Erik Panu, VP, Research & Development of the IP Group at Cadence. "The availability of Cadence VIP products supporting the latest standards facilitates a quick and convenient means for our customers to rapidly deploy the new 3D memory standards and to verify the correctness of their usage with SoC designs."