SAN JOSE, USA: Cadence Design Systems Inc. announced the Cadence Virtuoso Liberate AMS characterization solution, the industry's first dynamic simulation characterization solution for mixed-signal blocks such as phase-locked loops (PLLs), data converters, high-speed transceivers and I/Os.
Built upon the proven Cadence Liberate characterization platform, Virtuoso Liberate AMS characterizes post-layout netlists of mixed-signal macros with millions of associated parasitic elements 20X faster than traditional "divide and conquer" FastSPICE simulation methods and with true SPICE accuracy to enable accurate system-on-chip (SoC) signoff.
With the increasing complexity of SoCs, and the industry shift towards intellectual property (IP) reuse and digital-on-top design flows for signoff with static analysis tools, Liberty representations are required for all blocks in the design including mixed-signal macros.
To simplify this process, Virtuoso Liberate AMS automates standard Liberty model creation for large mixed-signal macro blocks by capturing the interaction between digital and analog paths and modeling it into a final Liberty library.
To increase throughput and reduce turnaround time from weeks to hours, Virtuoso Liberate AMS integrates Cadence's advanced FastSPICE technology, Spectre® XPS, and employs a unique hybrid partitioning approach to statically identify required arcs and dynamically exercise them to characterize large mixed-signal blocks.
This hybrid partitioning approach identifies circuit activity at the block level to carve out a critical-path partition for each logic arc and then characterizes each partition with true SPICE accuracy to create highly accurate library models.
For custom circuit designers, Virtuoso Liberate AMS is integrated with Virtuoso Analog Design Environment XL and leverages Virtuoso Analog Design Environment XL testbenches and setup to quickly move from circuit design validation into library generation.
"Prior to using Virtuoso Liberate AMS, the characterization process for mixed-signal blocks was an error-prone manual process," said Darren Engelkemier, VP of Digital IC Engineering, of Aquantia Corp. "With Virtuoso Liberate AMS, our design teams were able to automate this task by eliminating netlist processing and getting more accurate and reliable data especially for our custom cells with non-standard structures at circuit-level."
"Cadence is committed to providing its customers with world-class simulation and characterization solutions," said Tom Beckley, senior VP, Custom IC and PCB Group at Cadence. "Virtuoso Liberate AMS extends the company's leadership in mixed-signal flows, and gives designers a powerful new solution to increase their productivity and reduce their time to market."