BOSTON, USA, 2009 International Microwave Symposium: Freescale Semiconductor has expanded on its commitment to GSM EDGE wireless networks with the introduction of three high-performance RF power transistors based on laterally-diffused metal oxide semiconductor (LDMOS) technology.
The devices incorporate enhancements that make them easy to integrate into amplifiers while delivering exceptional levels of performance.
“As progress continues toward the delivery of third- and fourth-generation wireless services, GSM remains far and away the most widely deployed wireless technology,” said Gavin Woods, vice president and general manager of Freescale's RF Division. “Freescale’s newest RF power transistors are designed to help GSM carriers worldwide increase average revenue per subscriber by improving the efficiency of base station transceivers.”
MRFE6S9046N (920 to 960 MHz)
For GSM EDGE applications, the MRFE6S9046N operates from 920 to 960 MHz and delivers a 17.8 W average RF power output with 19 dB of gain, up to 42.5 percent efficiency and EVM of up to 2.1 percent RMS. It is housed in Freescale’s over-molded plastic package that combines precise mechanical tolerances and cost-effectiveness.
The package is also surface-mountable making it compatible with automated pick-and-place manufacturing, and enhanced internal impedance matching enables manufacturers to more easily accommodate printed circuit board variations. The internal output matching enables a user-friendly terminal impedance at the fundamental frequency, but also includes second and third harmonic terminations for higher efficiency, in line with the theory of Class F amplifiers.
MRF8S9100H/HS (920 to 960 MHz) and MRF8S18120H/HS (1805 to 1880 MHz)
These 28 V devices are designed for Class AB and Class C operation in GSM and EDGE systems. In GSM EDGE service, the MRF8S9100H/HS delivers 45 W average power gain of 19.1 dB and efficiency of 44 percent at 940 MHz, and EVM of 2.0 percent RMS.
In GSM EDGE service, the MRF8S18120H/HS delivers 46 W average power gain of 18.2 dB, efficiency of 42 percent at 1840 MHz and EVM of 1.7 percent RMS. The MRF8S9100H/HS and MRF8S18120H/HS are housed in rugged air-cavity ceramic packages.
The MRF8S9100H/HS can also be operated in the GSM 800 band, and the MRF8S18120H/HS supports operation in the GSM 1900 frequency band. All three devices are internally-matched to simplify circuit design, are RoHS compliant and contain internal ESD protection circuitry.
The MRFE6S9046N is in full production and samples are available. The MRF8S9100H/HS and the MRF8S18120H/HS are sampling now, with full production expected in July 2009. Reference test fixtures are also available with large-signal models expected in July 2009.
Showing posts with label GSM. Show all posts
Showing posts with label GSM. Show all posts
Tuesday, June 9, 2009
Friday, May 8, 2009
TriQuint, ZTE sign $50M agreement at US-China Business Forum
HILLSBORO, USA: TriQuint Semiconductor, a leading RF product manufacturer and foundry services provider, has signed a framework agreement with ZTE Corp.
The document states ZTE will procure TriQuint components, including but not limited to CDMA, GSM, and WCDMA ASICs, in the value of no less than $50 million dollars in CY 2009.
The agreement was formalized at the US-China Business Signing Ceremony: Partnering for Sustainable Economic Growth, April 28, 2009, in Chicago, IL. The event, aggregating $5.7 billion of US-China business through 28 contracts, was organized by the China Chamber of Commerce for Import & Export of Machinery and Electronic Products.
“We were delighted to be invited by ZTE to this event supporting international relations, and look forward to working with ZTE to further wireless communications,” said Ralph Quinsey, President and CEO of TriQuint Semiconductor. “Not only does this agreement strengthen the relationship of the two companies, but our innovations will bring high quality voice, data, and video communications to people everywhere.”
The document states ZTE will procure TriQuint components, including but not limited to CDMA, GSM, and WCDMA ASICs, in the value of no less than $50 million dollars in CY 2009.
The agreement was formalized at the US-China Business Signing Ceremony: Partnering for Sustainable Economic Growth, April 28, 2009, in Chicago, IL. The event, aggregating $5.7 billion of US-China business through 28 contracts, was organized by the China Chamber of Commerce for Import & Export of Machinery and Electronic Products.
“We were delighted to be invited by ZTE to this event supporting international relations, and look forward to working with ZTE to further wireless communications,” said Ralph Quinsey, President and CEO of TriQuint Semiconductor. “Not only does this agreement strengthen the relationship of the two companies, but our innovations will bring high quality voice, data, and video communications to people everywhere.”
Saturday, March 15, 2008
NXP India achieves RF CMOS in single chip
NXP Semiconductors India has developed the PNX4902, an ultra low-cost GSM/GPRS single chip, which was announced this February. The highlight -- the entire analog and RF work done has been in Bangalore! You might wonder what's so unique about this!
Well, let's start with what is tough about RF CMOS in single chip! CMOS is primarily a digital process. The analog circuit design in CMOS is tough, and the RF circuit design in CMOS is even tougher. Now, the co-existence of RF CMOS circuits with noisy digital in a single chip was (and is) considered the holy grail of chip design.
Next, cellular standards (such as GSM, EDGE) and specs are much tougher than other comparable standards like FM, Bluetooth, etc. Also, some key cellular parameters like RX sensitivity become tougher for single chips aimed at emerging markets. Especially, we all know that base stations are sparse in rural areas. Taking all of these as a whole -- RF design in presence of digital noise is the biggest challenge in a single chip!
Factors enabling single chip design
There are said to be three factors. One, RF CMOS is the high quality analog/RF design in CMOS. The high-performance RF blocks like LNA, mixers, etc., used to be the domain of BiCMOS, a higher cost technology. Next, fine-line CMOS (0.18mm and lower) provide high fT and lower noise.
Two, there are new architectures that minimize analog signal processing. Chip designers to convert the analog signal to digital -- so they might as well do it early -- analog-to-digital conversion at the IF, instead of at DC. There's also a need to move the final down-conversion and filtering into digital domain.
Three, the use of DSP to calibrate the analog performance. Things like temperature and process sensitivities in analog circuits need adjustments. Also, the digital engines can provide the ability to 'lock-in' the performance. Finally, a strong 'engineering culture' is a MUST to execute on complex chips.
Factors enabling AeroFone single chip design
NXP had acquired Silicon Labs Wireless group in 2007. Silicon Labs was a leader in RF CMOS, and so it also acquired numerous patents and trade secrets. Trade secrets for integration of RF CMOS circuits with noisy digital provide an edge over competitors as the integration intensifies.
Thereafter, NXP went on to form the NXP India single-chip design team. As single chip products are designed for emerging economies, NXP India invested heavily to develop the design expertise in Bangalore. The seed group of chip leads and system leads relocated from USA to India to start an analog/RF competency center for developing highly integrated chips.
The NXP India single chip design team has the vision to be the best center of competence in architecture and design of highly integrated circuits (ICs) for emerging market products. It is building the best analog/RF group in India.
Well, let's start with what is tough about RF CMOS in single chip! CMOS is primarily a digital process. The analog circuit design in CMOS is tough, and the RF circuit design in CMOS is even tougher. Now, the co-existence of RF CMOS circuits with noisy digital in a single chip was (and is) considered the holy grail of chip design.
Next, cellular standards (such as GSM, EDGE) and specs are much tougher than other comparable standards like FM, Bluetooth, etc. Also, some key cellular parameters like RX sensitivity become tougher for single chips aimed at emerging markets. Especially, we all know that base stations are sparse in rural areas. Taking all of these as a whole -- RF design in presence of digital noise is the biggest challenge in a single chip!
Factors enabling single chip design
There are said to be three factors. One, RF CMOS is the high quality analog/RF design in CMOS. The high-performance RF blocks like LNA, mixers, etc., used to be the domain of BiCMOS, a higher cost technology. Next, fine-line CMOS (0.18mm and lower) provide high fT and lower noise.
Two, there are new architectures that minimize analog signal processing. Chip designers to convert the analog signal to digital -- so they might as well do it early -- analog-to-digital conversion at the IF, instead of at DC. There's also a need to move the final down-conversion and filtering into digital domain.
Three, the use of DSP to calibrate the analog performance. Things like temperature and process sensitivities in analog circuits need adjustments. Also, the digital engines can provide the ability to 'lock-in' the performance. Finally, a strong 'engineering culture' is a MUST to execute on complex chips.
Factors enabling AeroFone single chip design
NXP had acquired Silicon Labs Wireless group in 2007. Silicon Labs was a leader in RF CMOS, and so it also acquired numerous patents and trade secrets. Trade secrets for integration of RF CMOS circuits with noisy digital provide an edge over competitors as the integration intensifies.
Thereafter, NXP went on to form the NXP India single-chip design team. As single chip products are designed for emerging economies, NXP India invested heavily to develop the design expertise in Bangalore. The seed group of chip leads and system leads relocated from USA to India to start an analog/RF competency center for developing highly integrated chips.
The NXP India single chip design team has the vision to be the best center of competence in architecture and design of highly integrated circuits (ICs) for emerging market products. It is building the best analog/RF group in India.
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