Intel unveils 45nm SoC for Internet TV

INTEL DEVELOPER FORUM, SAN FRANCISCO, USA: Intel Corp. today unveiled the Intel Atom processor CE4100, the newest SoC in a family of media processors designed to bring Internet content and services to digital TVs, DVD players and advanced set-top boxes.

The CE4100 processor, formerly codenamed "Sodaville," is the first 45nm-manufactured consumer electronics (CE) SoC based on Intel architecture. It supports Internet and broadcast applications on one chip, and has the processing power and audio/video components necessary to run rich media applications such as 3-D graphics.

"Traditional broadcast networks are quickly shifting from a linear model to a multi-stream, Internet-optimized model to offer consumers digital entertainment that complements the TV such as social networking, 3-D gaming and streaming video," said Eric Kim, senior vice president and general manager, Intel Digital Home Group. "At the center of the TV evolution is the CE4100 media processor, a new architecture that meets the critical requirements for connected CE devices."

CE industry rallies around Intel CE media processors
Joining Kim on stage during his keynote were executives from Adobe Systems, BBC (British Broadcast Company), CBS, Cisco and TransGaming. These and other companies are working with Intel to advance content, services and infrastructure for connected CE devices.

As TVs become more interactive, Adobe Flash is an important enabling technology to help content developers blend together video, 3-D animation and rich graphics. Intel is working with Adobe to port Adobe Flash Player 10 to the family of Intel CE media processors to optimize the playback of graphics and H.264 video to enable for the first time a wide array of Flash-based content on the television.

"The architecture of Intel media processors provides a powerful and innovative platform to showcase Flash-based applications in a vivid way," said David Wadhwani, general manager and vice president, Platform Business Unit at Adobe.

"Flash Player 10 combined with the performance of the Intel media processor and its support for standards such as OpenGL ES 2.0 offers a compelling environment for Flash-based games, videos and other rich Web content and applications." The companies expect Adobe Flash Player 10 to be available in the first half of 2010 for Intel media processor-based CE devices.

Malachy Moynihan, vice president for video product strategy, Cisco Service Provider Video Technology Group, discussed how delivering premium video to the TV will require intelligent networks and content storage.

"Cisco is helping service providers evolve their networks to a medianet, integrating the best elements of the existing broadcast infrastructure with carrier-grade IP networks to provide new services like unified video experience," said Moynihan.

"The crucial components to enable a unified video experience include the need for an emerging monetization model across the video ecosystem as well as client devices with quality graphics and a high-performance processor to truly enhance the visual appeal for consumers."

On-demand gaming for TV
TransGaming President and CEO Vikas Gupta announced an on-demand gaming service called GameTree.tv to be optimized for connected digital TVs and CE devices powered by Intel media processors.

"At TransGaming, we're in the business of enabling existing games to operate on alternative operating systems," said Gupta. "Since Intel CE processors run on Intel architecture, it's a fast and easy migration from the PC to the CE platform."

The GameTree.tv service will offer a broad library of games such as sports, action and adventure and provide content developers with a software development kit to support the migration of existing games and the development of new games based on the Intel CE platform. It will help revolutionize the delivery and global consumption of video games and provide a turnkey monetization strategy for CE manufacturers and cable/satellite providers (MSOs).

TV widgets, interactive TV applications
Intel CE media processors provide a full-featured software framework called Widget Channel for the development of Internet applications, or TV widgets. Broadcast networks such as CBS are expanding the gallery of TV widgets to help their viewers find and connect to premium content in a more personalized manner.

"Navigation is the No. 1 challenge for today's television viewers," said George Schweitzer, president, CBS Marketing. "Intel's CE technology and our new TV Widget platform are designed to help people find the shows they want and discover new programs that are relevant to their interests. What's more, the TV Widget gives us another platform to connect and interact with our audience while delivering an exciting new television experience."

Intel is working with the industry to expand Widget Channel to provide consumers a range of services such as movies, music, games and personal videos. TV Widgets and services shown at IDF were from Accedo Broadband*, The Associated Press*, BIGSTAR.tv*, CBS*, CinemaNow*, Dailymotion*, Immediatek*, Mediafly, MyVideo*, Netflix*, PlayJam*, RadioTime*, RallyPoint*, ShowTime Networks*, Tagesschau* and WhereverTV.*

Intel Atom processor CE4100
The CE4100 processor can deliver speeds up to 1.2GHz while offering lower power and a small footprint to help decrease system costs. It is backward compatible with the Intel Media Processor CE 3100 and features Intel Precision View Technology, a display processing engine to support high-definition picture quality and Intel Media Play Technology for seamless audio and video.

It also supports hardware decode of up to two 1080p video streams and advanced 3-D graphics and audio standards. To provide OEMs flexibility in their product offerings, new features were added such as hardware decode for MPEG4 video that is ready for DivX Home Theater 3.0 certification, an integrated NAND flash controller, support for both DDR2 and DDR3 memory and 512K L2 cache.

The CE SoC contains a display processor, graphics processor, video display controller, transport processor, a dedicated security processor and general I/O including SATA-300 and USB 2.0.

Renesas selects Synopsys Proteus OPC for 45-nm node production

MOUNTAIN VIEW, USA: Synopsys Inc. announced that Renesas Technology Corp., the world's No.1 supplier of microcontrollers and one of the world's premier semiconductor system solutions providers for mobile, automotive and PC/AV (Audio Visual) markets, has adopted Synopsys Proteus OPC for 45-nanometer (nm) production.

With the introduction of 45-nm and below technologies, the demand for optical proximity correction (OPC) becomes greater due to design complexity and layer volume, making time to market and cost of ownership critical factors in OPC vendor selection. Proteus OPC is the industry's most cost-effective solution, since its highly scalable engine runs on standard hardware.

"At Renesas, we are faced with the challenge to tape out large volumes of 45-nm designs with severe schedule constraints," said Hitoshi Sugihara, department manager, DFM & Digital EDA Technology Dept., Design and Development Unit at Renesas Technology Corp. "We selected Proteus OPC since it meets our technology, schedule, and costs requirements. This decision will enable us to sustain our leadership in microcontrollers and semiconductor system solutions."

Proteus delivers near-linear scalability so that designers can efficiently utilize hundreds of cores, allowing them to balance turnaround-time with cost. Proteus is the only tool that enables users to effectively manage technology requirements, turnaround time and cost through the inclusion of both frequency- and space-domain simulation engines.

With this capability, users can deploy the more accurate frequency-domain engine for the most critical layers and utilize the faster space-domain engine for the non-critical layers. ProGen, Proteus' highly customizable solution calibrates a single model that is utilized by both the space- and frequency-domain engines.

"As a leading semiconductor system solutions provider focusing on cutting-edge designs, Renesas has a critical need for an OPC solution that reduces turnaround time and cost," said Howard Ko, senior vice president and general manager of the Silicon Engineering Group at Synopsys. "Renesas' adoption of Synopsys Proteus OPC is proof that Synopsys' technology is the best solution to address these advanced design requirements."

SMIC achieves silicon success with high performance 45nm process

SHANGHAI, CHINA: Semiconductor Manufacturing International Corp. announced the successful completion of its first 45-nanometer high performance (GP, generic process with high performance) yield lot.

SMIC's high-speed, high performance 45nm GP technology integrates a silicon germanium stress module into the design, allowing the device to run faster, making it ideal for a number of applications, including system-on-chip, graphics and network processors, telecommunications and wireless consumer products, and serves as a technology platform for the fast growing China market.

The 45nm GP technology bookends with SMIC's silicon success on its 45nm low power (LP) technology, which is suitable for mobile devices that put a premium on low power consumption. SMIC signed an agreement with International Business Machines (IBM) to license its low-power and high-performance bulk CMOS technologies in December 2007. The GP technology transfer was completed in March 2009.

"I'm delighted with the progress of SMIC's 45nm project team, which continues to meet rigorous deadlines, and we appreciate the excellent support from IBM throughout this progress," said Dr. Robert Tsu, SMIC's 45nm project leader and Associate Vice President of Logic Technology. "Integrating the silicon germanium process and achieving a well-yielded test chip from the very first yield lot is a significant technical accomplishment, and these accomplishments allow SMIC to provide a highly manufacturable technology to our customers."

SMIC's 45nm GP technology is supported by a proven design-in SPICE model and in-house design IP capability that enables customers to begin prototype product design and plan for early time-to-market. In June, SMIC announced the adoption of new SPICE model software for the design and verification of 45nm IP blocks, I/O circuitry, and standard cell characterization flows.

As the company's 65nm low-power technology development cycle comes to a successful close, with a recently completed IP portfolio, multiple customer product qualification, and a ramping up of production, efforts have focused on 45nm. The readiness of SMIC's 45nm LP and GP technologies for design-in allows customers to enter a premium-value market.

"We are very excited and encouraged by the completion of our first 45nm high performance yield lot, another important signpost in SMIC's strategic plan," said Dr. Richard Chang, SMIC's President and CEO.

"It verifies the IBM-licensed technology, validates our strategic decision to invest in advanced logic technologies, and enhances SMIC's position as the advanced logic technology leader in China. This 45nm GP process is a proven, robust, high yielding, and high performance technology that we anticipate can not only deliver better performance, reliability, and cost to our valued customers, but also help SMIC become even more competitive in China and worldwide."

Samsung intros 45nm application processor for next gen CE devices

SEOUL, KOREA: Samsung Electronics Co. Ltd announced the latest in its popular, ARM11 series of application processors, the S5P6440. Designed using Samsung's advanced 45nm low power CMOS process technology, the S5P6440 offers a low power, high performance, and cost effective solution for consumer electronic (CE) products such as personal navigation devices (PND).

"Today's ultra-competitive consumer electronics market demands rapid performance upgrades and effective cost reduction to continue its expansion," said Dr. Kwang-hyun Kim, Senior VP of Sales and Marketing at Samsung Electronics' System LSI division.

"Our S5P6440 application processor is specifically designed with those objectives in mind to offer substantial improvements in CPU performance at low power, high quality graphics capability, and lower system BOM cost. CE device manufacturers using S5P6440 can offer exciting new products such as next generation PND to the market in a timely manner."

Samsung's S5P6440 is based on an ARM1176 CPU core which runs at either 533 MHz or 667MHz clock speed. The CPU core and all on-chip hardware accelerators and peripheral interfaces are connected through a 64-bit AXI bus running at 166MHz, allowing ample input/output bandwidth for handling the multiprocessing requirements in real-life applications.

The S5P6440 features 2D graphics acceleration hardware that is compliant with the OpenVG application programming interface (API) standard. The OpenVG API standard enables advanced graphics functions such as alpha blending for transparency effects, anti-aliasing for sharper graphics, and vector graphics support for scaling without loss of image quality. Utilizing this graphical capability, devices implemented with the S5P6440 can offer a vivid graphical user interface that greatly enhances the user experience.

To lower the system BOM cost and ease the design complexity, the S5P6440 incorporated various interface hardware IP. An advanced NAND error correction hardware is included to support current and next generation MLC NAND flash devices which offer higher storage density at a lower cost.

The S5P6440 also integrated a DRAM memory controller that supports both mobile DDR (mDDR) as well as the lower cost DDR2 memory chips, allowing device manufacturer's different choices of storage device types to meet different market segments' requirements.

In addition, the S5P6440 integrated a mobile industry processor interface (MIPI) display serial interface (DSI) for advanced graphics and display capabilities at low power. The MIPI DSI interface is valuable to customers wanting to reduce the complexity of the display interface by reducing the number of pins, which has benefits in terms of design simplicity and cost.

MIPI DSI also uses a differential signal which substantially reduces EMI issues. These advantages are increasingly important for mainstream connected CE products where noise interference among electronic components in within a product can adversely affect the product's performance.

Samsung's new S5P6440 application processor supports all major high-level operation systems including WinCE and Linux. This allows OEMs and PND manufacturers to differentiate their products through a rich, easy-to-use, customizable user interface, as well as robust, flexible application architecture.

The S5P6440 application processor is sampling to key customers now and is scheduled for volume shipment in the third quarter of this year. The chip is housed in a 13x13 FBGA package with a ball pitch of 0.65mm.

Qualcomm expands Snapdragon platform for smarter smartphones, smartbooks

TAIPEI, TAIWAN: Qualcomm Inc. is expanding the Snapdragon platform with a next-generation chipset that uses 45nm process technology to provide faster processing, significant battery life improvements and other enhancements for the user experience on Snapdragon-powered smartphones and smartbooks.

The new Snapdragon QSD8650A chipset -- scheduled for sampling before the end of 2009 -- offers significant performance improvements including a 1.3 GHz processor for 30 percent higher performance as well as enhanced multimedia and 2D/3D graphics. Using 45nm also allows power consumption improvements such as up to 30 percent lower dynamic power than previous-generation Snapdragon products and an unmatched standby power of less than 10 millwatts.

“This latest addition to the growing family of Snapdragon chipsets will help our customers to develop faster, more power-efficient smartphones and smartbooks,” said Luis Pineda, senior vice president of marketing and product management at Qualcomm CDMA Technologies. “This new 45 nm device shows our continued commitment to extending the capabilities of the Snapdragon platform with leading-edge process technology and an expanded list of integrated features.”

The QSD8650A chipset offers an exceptionally high level of integration. In addition to its faster processor and faster bus speed, the new QSD8650A chipset also offers multi-mode UMTS and CDMA 3G mobile broadband connectivity in the same 15x15mm package as current Snapdragon chipsets.

A standalone, power-efficient 2D graphics accelerator and enhanced 3D graphics core deliver a powerful multimedia experience with better performance of Adobe Flash software. It also features integrated GPS and high-definition video recording and playback, the latest Bluetooth 2.1 technology and support for Wi-Fi, high-resolution WXGA displays and mobile TV technologies such as MediaFLO, DVB-H and ISDB-T.

In addition to the new QSD8650A chipset, Qualcomm's Snapdragon family includes the original 1 GHz QSD8x50 chipsets and the 45nm QSD8672 chipset with dual CPUs capable of up to 1.5 GHz for even faster response and processing. More than 15 manufacturers are now developing more than 30 Snapdragon-based products, the first of which is the Toshiba TG01 Smartphone, introduced in February 2009.

Synopsys launches IC Validator DRC/LVS solution

MOUNTAIN VIEW, USA: Synopsys Inc. today announced the IC Validator DRC/LVS solution for in-design physical verification and signoff for advanced designs at 45nm and below.

Architected to deliver the high accuracy necessary for leading-edge process nodes, superior scalability for efficient utilization of available hardware, and ease-of-use, IC Validator provides a step up in physical designer productivity.

IC Validator can significantly reduce total physical verification time through in-design verification, stream-out reduction, incremental processing, automatic error detection and fixing, and near-linear scalability across multiple CPU cores. IC Validator is production ready, having been included by TSMC for the company's EDA qualification program of design rule checking/layout verification signoff (DRC/LVS) starting from 28nm.

"TSMC employs rigorous qualification criteria to help ensure DRC/LVS accuracy for signoff physical verification. We have worked closely with Synopsys during the development of IC Validator and have included it in our 28nm EDA qualification program," said S.T. Juang, senior director of design infrastructure marketing at TSMC. "Such a collaboration with Synopsys has produced good results with IC Validator in TSMC's most current physical verification EDA qualification report."

Prevailing approaches to physical design today can be described as 'implement-then-verify,' and result in multiple iterations between design and signoff. At leading-edge nodes like 45nm and below, the implement-then-verify approach can be slow and may complicate convergence as layout corrections can alter design objectives such as area, timing, and power.

In-design physical verification brings the full physical verification constraints into the design phase, helping to ensure clean layout upon leaving the design environment and avoiding late-stage surprises close to tapeout. With in-design verification, specific errors and selected areas of layout can be targeted incrementally, providing a speed-up in overall design completion time.

In addition, the IC Validator can automatically discover and fix design rule violations within the global context of the design. Operations typically performed during physical verification, such as metal fills, may trigger additional design changes to achieve timing closure.

Working in concert with IC Compiler, IC Validator's in-design flow dramatically reduces such iterations by performing signoff-quality, timing-driven metal fill during the design phase.

"Our customers have identified the need for faster DRC/LVS at advanced nodes, and the need for bringing physical verification capabilities into the implementation flow early to mitigate iterations which can seriously impact time-to-tapeout," said Antun Domic, senior vice president and general manager, Synopsys Implementation Group. "In-design physical verification with IC Validator, combined with its accuracy and efficient handling of the ever-increasing design-rule complexity, will significantly reduce the overall physical design cycle time for our customers."

Cadence Encounter system used by Gennum’s Snowbush IP Group

SAN JOSE, USA: Cadence Design Systems Inc. announced that Gennum Corp.'s Snowbush IP Group utilized the Cadence Encounter Digital Implementation System to develop the industry’s first 45-nanometer SuperSpeed USB 3.0 PHY IP core.

Encounter was used for timing closure and layout on the digital portion of the PHY. Introduced in March, the new IP from Gennum’s Snowbush IP Group features an integrated USB 3.0 PHY and controller IP with a 5-gigabit per second (Gb/s) transfer rate in each direction. The Encounter Digital Implementation System helped Gennum’s Snowbush IP design team quickly target the digital portion of the PHY to advanced 45nm and 40nm process technologies at multiple foundries, further expanding its market potential.

“The high-speed timing constraints of the PCS layer of the new USB 3.0 PHY require the highly capable design methodology offered by Encounter,” said John Wilby, director of engineering-PHY, for the Snowbush IP Group at Gennum. “The move from a competitor’s design environment to the Cadence Encounter Digital Implementation System took just three months from installation to first-pass silicon success. Key benefits with Encounter include its native signoff quality timing closure and support for advanced DFM rules in deep submicron technologies. In combination with low-power signoff, we also gained improved productivity, a high quality of silicon and ultimately faster time to market.”

Wilby also noted that the fully integrated Encounter Digital Implementation System allowed Gennum to raise the bar on its design specifications and improve the competitive differentiation of its customizable family of IP cores through improved power savings and chip performance, reduced jitter, and optimized noise immunity.

The Encounter Digital Implementation System is a configurable and extensible high-performance, high-capacity, scalable design solution uniquely delivering flat and hierarchical design closure and signoff analysis, as well as low-power, advanced-node, and mixed-signal design solutions in a single integrated environment. The system also delivers interoperability with package, logic, and custom IC design. Cadence design-for-manufacturing (DFM) technologies are an integral part of the Encounter Digital Implementation System, enabling early identification, analysis and repair of yield-limiting design elements present at advanced nodes.

“Gennum’s Snowbush IP Group has a strong track record of success, and we’re pleased to play an integral role in the development of its latest high-speed family of customizable IP cores,” said Chi-Ping Hsu, senior vice president of implementation research and development at Cadence. “This project was a success on multiple levels, but most notably it demonstrated that a full front-to-back design solution can be installed, ramped and used to deliver state-of-the-art advanced-node, low-power designs in a fraction of the time of previous solutions, with first-pass silicon success, lower risk, and faster time to market as the reward.”

NXP India's Rajeev Mehtani on top trends in global/Indian electronics and semicon!

When a new year approaches, we start analyzing the year gone by and try to gauge what could happen in the coming year. This really holds true, as far as the technology industry is concerned.

It's been a week since I've been mulling over these myself, especially, pondering over developments in the global semiconductor and electronics industries, as well as what could happen in India during 2009. Well, lots will happen, and I can't wait for the new year to start!

I caught up with Rajeev Mehtani, vice president and managing director, NXP Semiconductors, India, and discussed in depth about the trends for 2009. Here's a look at that discussion.

INDIA -- ELECTRONICS & SEMICONDUCTORS

1. The DTH story will continue to increase in India with companies such as Tata Sky, DISH TV, BIG TV, etc., gaining market share. Owing to these challenges, there would be significant consolidation among the cable operators. Digitalization will also be seen in 2009.

2. The slowdown will affect growth across all sectors. Our view is that LCD TVs as well as STBs will continue to grow.

3. The year 2009 will witness e-commerce revolution and the RFID sector will grow at a 40-50 percent clip. The government has been sponsoring a lot of projects, which include RFID in the metros, e-passport cards and national ID cards. By mid-2009, we can expect a mass deployment of these projects as well as micro payments.

4. Manufacturing in India will continue to grow; EMS or OEMs, such as Samsung, Nokia, Flextronics, etc.

5. There could be a move from services to products in electronics and semiconductor spaces. The number of funded startups has grown significantly over the last years and more and more ideas are coming on the table.

6. The solar/PV sector will grow in India. High entry cost of capital for panels will be a barrier for this sector. Government enhancement is necessary. India will be different than other countries as people won't push energy back into the grid; it will be used more for household consumption. The India grid is unstable. Tracking it requires a lot of expensive electronic switching. Solar deployment could be at the micro level, and also community level, where it makes more sense.

7. The startups in India are mostly Web 2.0 based, although there aren't many hardware startups.

GLOBAL -- ELECTRONICS & SEMICONDUCTORS

1. The semiconductor industry is truly global, That is mostly because it is a very expensive industry.

2. Things are a bit murky in the semiconductor industry. It would probably be dipping 10-15 percent next year.

3. Globally, energy management and home automation will start to take off in 2009. Satellite broadcasters will also continue to gain more strength.

4. On a worldwide scale, 3G will win. You will have 3G phones, and you'd add LTE to those. India is slightly different. Only 20 percent of Indian households are ready for broadband access. In India, WiMAX could be a way to have wireless broadband at home.

5. Industries moving to 300mm fabs will be making up only 20-25pc of the market. Not many need 45nm or 40nm chips. People will question any major capex, until there's a big return and wait for recession to end. The bright spot is solar!

6. The fabless strategy would be the only way to go forward. While MNCs with fabless strategy are present in India, Indian startups in this space are quite few.

AMD's roadmap 2009 provides lots of answers... now, to deliver!

AMD's roadmap 2009, or guidance, presented during its 2008 Financial Analyst Day on Nov. 13th, provided a lot of answers to several of the questions it had been facing. Also, AMD did something Intel hasn't! It did not revise the Q4 guidance!! During a webcast, AMD CFO, Bob Rivet, said he would offer an update to the company’s earnings outlook in the first week of December. Also, one of AMD's announcements, the Yukon, is definitely not going to take on Intel's Atom, and should be priced higher.

Kicking of proceedings, Dirk Meyer, President and CEO, talked about a complete AMD & Foundry Company realignment, which includes executing key technology transitions. These include: deliver 2nd wave of 45nm products and platforms -- including chipsets; transition to 40nm graphics products; finalize 32nm designs for 2010 production. Also, deliver, market and sell platforms; and continue operational excellence.

Later, during the Q&A session, when asked about the validity of AMD's cross-license for patents with Intel, Meyer said there was no legal issue. AMD's agreement with Intel allows AMD subsidiaries to be licensed. The Foundry Company, 43.5 percent owned by AMD, qualifies as a subsidiary, as defined, as per the agreement with Intel.

Asset Smart strategy
According to Rivet, who spoke last during the Webcast, it has been a tough operating environment. However, AMD launched Asset Smart; achieved operating profitability in Q3-08 and is now making progress toward $1.5B operating income breakeven by early ‘09. It also has a richer MPU product mix and the first 45nm product has been launched. Graphics has returned to operating profitability. AMD has already divested its DTV business and plans to sell handheld.

Asset Smart manufacturing strategy
* Strategic commitment from Mubadala
* The Foundry Company plans multi-billion dollar build-out of leading edge fabs in Dresden and Upstate New York
* Expanded IBM partnership delivering leading-edge bulk and SOI process technology

Stronger financial structure
* ~$1B new cash investment
* ~$1.2B debt assumed by The Foundry Company
* Future fab capital expenditures optional
* Reduced process technology R&D costs
* Improved free cash flow by elimination of required fabrication capital expenditures offset somewhat by wafers purchased for cash (foundry model)
* Leaner and more variable business model, with a lower breakeven point of ~$1.5B

The Foundry Company
Doug Grose, Senior VP, Manufacturing & Supply Chain Management and Incoming CEO, The Foundry Company, highlighted AMD's 2009 manufacturing priorities. These are: transition to best-in-class foundry model; complete conversion to 45nm production; and successful 32nm technology development.

This October 7, AMD and the Advanced Technology Investment Co. announced their intention to create a new global enterprise, The Foundry Company, to address the growing global demand for independent, leading-edge semiconductor manufacturing. This announcement was the lynchpin of AMD’s Asset Smart plan, and a key initiative designed to enable the company to achieve sustainable profitability.

At the 2008 AMD Financial Analyst Day event, AMD provided more details on what its manufacturing operations will look like once the spin-out of The Foundry Company is complete.
* For the Silicon on Insulator (SOI) and bulk manufacturing processes needed to build AMD CPUs and APUs, The Foundry Company plans to offer AMD 65nm, 45nm and 32nm manufacturing capabilities at:
- Fab 36 (Dresden)
- Fab 38 (Dresden)
- Fab 4x (Saratoga County, NY)
* For the bulk manufacturing processes AMD uses to manufacture its chipsets and GPUs, AMD plans to have access to 55nm, 40nm and 32nm manufacturing capabilities at:
- TSMC/UMC (Taiwan)
- Fab 38 (Dresden)
- Fab 4x (Saratoga County, NY)
* The Foundry Company also provided an update on its progress towards moving to a new 32nm manufacturing process for bulk and SOI production. The company confirmed that it will complete 32nm test chips in Dresden by the end of year, and is on schedule to successfully incorporate High-k Metal Gate within this process node. 32nm technology development will ramp in late 2009 in preparation for 1H 2010 volume production.

Platforms for ultraportable notebooks and mini-notebooks
There has been lot of interest in ultraportable notebooks and mini-notebooks, owing to their small form factor and lightweight profile. AMD also announced new platforms aimed at serving these markets.
* AMD introduced two ultraportable notebook platforms -- Congo and Yukon. Congo is based on the dual-core Conesus CPU with the RS780M and SB710 chipset. Yukon is based on a single-core CPU with the RS690E and SB600 chipset. While targeted at the ultra-portable market, these platforms are designed to address a portion of mini-notebook market, especially at the dissatisfied users of limited Internet experience of mini-notebooks. Yukon is planned to be available in 1H09 followed by Congo in 2H09.
* AMD announced the 2010 ultraportable notebook platform code named Nile. It will feature dual-core Geneva CPU utilizing DDR3.
* In 2011, AMD plans to introduce the dual-core Ontario APU for ultraportable and mini-notebook platforms.

Server platforms
* Fiorano, the first AMD platform to combine AMD server processors and chipsets. It is on schedule for mid-2009 introduction based on planned release of the AMD SR5690 chipset. Fiorano will likely support Shanghai and the upcoming six-core Istanbul processor in 2H09.
* AMD's next-generation, DDR3-based server platform, Maranello, remains on track for introduction in 1H10.

Desktop platforms
* Dragon is set to launch in Q1 2009 and feature AMD's upcoming 45nm AMD Phenom II X4 quad-core processors, codenamed Deneb.
* Kodiak is scheduled to enhance AMD Business Class platforms in 2H09.
* Pisces mainstream desktop platform will debut in 2H09.
* Maui is its new home theater platform planned for launch in Q408.

There you have it! Everyone wants the global semiconductor industry to be humming and chirping! It would be great if AMD delivers on its promise and hopefully, becomes profitable all over again as well.

For those keen, PDF files of all of AMD's presentations can be downloaded from its web site.

The 'Bangalore' in Shanghai! But AMD still has lots of questions to answer!!

Welcome Shanghai, AMD's latest 45nm quad-core Opteron processor! It was launched with great fanfare in Bangalore today. However, lots of other questions remain unanswered. It is hoped that some answers will come out of AMD's 2008 Financial Analyst Day, which starts later today, in the US. More of those questions later!

First, the chip maker focused on three key points: virtualization performance; delivering up to 35 percent more performance and up to 35 percent decrease in power consumption at idle; and up to 21 percent CPU power savings.

Shanghai is packed with a lot of virtualization features, evidently aimed at the enterprise segment. It allows faster switching between virtual machines. Among other features, Shanghai allows live migration, which was also demonstrated at the launch,
and the cache has been doubled to 8MB. As per the AMD spokespersons, the Shanghai platform already boasts of over 25 ready platforms and more platforms will be announced by its customers in the coming months. It is said that with the Shanghai, AMD is well positioned in the 2P market.

The 45nm quad-core AMD Opteron processors build on AMD's legacy as the virtualization platform of choice, with the new processor already powering nine global OEM servers specifically designed for virtualization. The processors deliver faster 'world switch' time, which enhances virtual machine efficiency, and feature improved Rapid Virtualization Indexing, AMD's innovation in AMD-V that reduces the overhead associated with software virtualization.

On the energy efficiency side, AMD's Smart Fetch technology reduces power consumption by allowing cores to enter a 'halt' state during processing idle times with zero impact on application performance and compliments AMD's CoolCore technology, which reduces power on unused sections of each processor to further reduce power consumption. Shanghai supports DDR2, and not DDR3, for now!

The 'Bangalore' in 'Shanghai'
You can see Karthik Muttuswamy, Silicon Design Head, AMD India, Bangalore, along with others, holding the wafer in the picture above. Karthik's team was involved in all aspects of Shanghai, from architecture to tapeout. Shanghai was developed across Centers of Excellence in the United States and India. The US/India teams delivered key sections of the chip. AMD India's Bangalore team put them all together to create the complete design.

It is a matter of really great pride that India is playing a decisive role in driving the roadmap for the next generation processors and has contributed tremendously to the latest 45nm server processors, he said.

Lots of unanswered questions for AMD!
Well, AMD surely has managed to bring Shanghai faster to the market than expected. It is said to be the only X86 MPU spanning the 2P, 4P and 8P server segment. So far so good! There are lots of questions that AMD has to answer! (Oh, I did ask three of these questions!)

Now, where is that Atom killer? Where is AMD's strategy in the netbooks and mobile Internet devices spaces (MIDs)? Don't tell those aren't important for them, with rival Intel going for broke in that segment! Where is AMD's strategy, then, for OEMs to push its technologies into much smaller form factors?

What about Abu Dhabi-based Advanced Technology Investment Co. and The Foundry Company? How will this deal proceed given AMD's cross-licensing agreement with Intel? Or, how will the foundry compete against the likes of TSMCs of this world? Will the Shanghai bring about a brilliant or much better Q4 for AMD? What's the projection like? And well, how will the Shanghai strengthen AMD's position in the MPU segment? How will AMD fare in the global semiconductor industry next year?

I also thought that AMD would probably touch upon embedded computing, but well, nothing of that sort, as this was a Shanghai launch. Maybe, that'll come later!

It is hoped that a lot of answers to these questions, and much more, will come out at the Financial Analyst Day later today.

Mentor Graphics: DFM is where all the value is!

As promised, here is the concluding part of my discussion with Joseph Sawicki, vice president & GM, Design to Silicon Division, Mentor Graphics.

We went over the design for manufacturing (DFM) challenges and how yield can be improved. He also touched upon the design challenges in 45nm and 32nm, respectively.

Given that the semiconductor industry does speak a lot about DFM, what steps are being taken to improve on the overall yield?

According to Sawicki, in the VLSI microchip era, yields started at 60-70 percent, and so DFM wasn't required. However, in the nanochip era, DFM is where all the value is. [VLSI Research.]

Joseph Sawicki, vice president & GM, Design to Silicon Division, Mentor GraphicsHe added that at smaller geometries, manufacturing variability has a much greater impact on timing, power dissipation, and signal integrity. Traditional guardbanding is no longer sufficient to guarantee competitive performance at acceptable yields, and excessive design margins erase the advantages sought by going to the next node in the first place.

Moving to advanced technologies without dealing effectively with manufacturing variability can actually put a design at a competitive disadvantage due to low parametric yield.

"Successful IC implementation requires a detailed understanding of how variability affects both functional and parametric yield. Customers need a manufacturing-aware engineering approach that extends across the entire physical implementation life cycle, starting with cell library development and extending through place and route, physical verification, layout optimization, mask preparation, testing, and failure analysis.

"They need a design flow that helps them "co-optimize" for both performance and yield simultaneously, based on accurate models of manufacturing process variability. The ability to do this quickly and effectively can give IC designers a powerful competitive advantage," Sawicki said.

There is no silver bullet! It takes a broad-based, well-integrated approach to have a significant and consistent impact on manufacturability.

According to him, Mentor Graphics provides a complete manufacturing-aware design-to-silicon solution addressing random particle effects, small-scale device and interconnect interactions, lithographic distortions and process window variations, and thickness variations resulting from chemical-mechanical polishing (CMP) and variable film deposition and etch rates.

"Our tools incorporate comprehensive, highly-accurate models that have been tuned and verified for specific manufacturing environments, and address every stage of the digital IC implementation life cycle," he added.

So, how is Mentor handling 45nm and 32nm design challenges?

Sawicki added: "Advanced process nodes present challenges at every stage of IC implementation, from place-and-route, through physical verification, layout enhancement, testing and yield analysis. Mentor has a complete design-to-silicon flow that addresses the critical challenges of IC implementation at every stage."

Mentor on EDA trends and solar/PV

This is a continuation of my recent discussion with Joseph Sawicki, vice president & GM, Design to Silicon Division, Mentor Graphics.

There have been whispers that the EDA industry has been presently lagging behind semiconductors and is in the catch-up mode. "That’s a matter of perspective. There are definitely unsolved challenges at 32nm and 22nm, but the reality is that we are still in the technology development stage," he says.

For EDA tools that address implementation and manufacturing issues (i.e., Mentor design-to-silicon products), there are dependencies that cannot be fully resolved until the process technology has stabilized. Mentor Graphics is laying the groundwork for those challenges and working in concert with the process technology leaders to ensure that our products address all issues and are production-worthy before the process technology goes mainstream.

On the other hand, although Mentor’s products are fully-qualified for 45nm, there have only been a handful of tapeouts at that node, so for the majority of customers, we are ahead of the curve.

On ESL and DFM as growth drivers
ESL and DFM are said to be the new growth drivers. Sawicki adds: "As Wally Rhines has said in his public presentations, system level design and IC implementation are the stages of development where there are the most challenges, and therefore the most opportunities. To continue the traditional grow spiral that the electronic industry has enjoyed as a result of device scaling, we need more sophisticated EDA solutions to deal with both of these challenges."

ESL is responding to the growth of design complexity and the need for earlier and more thorough design verification, including low power characteristics, and software integration.

The Design-to-Silicon division is addressing the issues of IC implementation which result not only from the increase in design complexity and devices sizes, but also from increasing sensitivity of the manufacturing process to physical design decisions, a phenomenon often referred to as “manufacturing variability.”

Although the term “Design-For-Manufacturing” reflects the need to consider manufacturability in design and to optimize for both functional and parametric yield, it is important to emphasize that DFM is not simply an additional tool or discrete step in the design process, but rather an integration of manufacturing process information throughout the IC implementation flow.

With single threading, we can no longer handle designs over 100 million gates. Of course, at 45nm, you can do a 100mn gates. That rewriting process is another issue that is also slowing out. It would be interesting to see how is Mentor handling this.

According to Sawicki, Mentor has incorporated sophisticated multi-threading and multi-processing technologies into all of its performance-sensitive applications, from place-and-route, through physical verification, resolution enhancement and testing.

He says, "Our tools have a track record of impressive and consistent and performance and scalability improvements, which is why we continue to lead the industry in performance."

In addition to merely adding multi-threading and support for multi-core processors, Calibre products have a robust workflow management environment that automatically distributes the processing workload in the most efficient manner across any number of available clustered computing nodes.

Mentor's Olympus-SoC place-and-route is inherently scalable due to its advanced architecture which includes an extremely efficient graph representation for timing information, and a very concise memory footprint. In addition, all the engines within Olympus-SoC can take advantage of multi-threaded and multi-core processors for high performance. These features enable Olympus-SoC to handle 100M+ gates designs in flat mode without excessive turnaround time.

Mentor’s ATPG tools are also designed to operate in multiprocessing mode over the multiple computing platforms to reduce test pattern generation time. In addition, Mentor test pattern compression technology reduces test pattern volume and test time, making it feasible to fully test 100M gate devices and maintain product quality without an explosion in test cost.

With EDA is starting to move up to the system level, will this make EDA less dependent on the semiconductor world?

Sawicki agrees that there are challenges at both the front end and back end of the electronic products design and manufacturing life cycle. Both of these opportunities are growing. In addition, developments like multi-level (3D) die packaging, through-silicon via (TSV) structures and other non-traditional techniques for device scaling are pushing system and silicon design issues closer together.

Reaching the 22nm node will require highly compute intensive EDA techniques for physical design to compensate for limitations in the manufacturing process. Beyond that, we could see a major shift to new materials and manufacturing techniques that would open new green fields for EDA in the IC implementation flow.

EDA going forward
How does Mentor see the EDA industry evolving, going forward?

Sawicki adds: "There are three key trends to watch. Firstly, for design to remain affordable at the leading edge, we need to enable radical increases in productivity. Electronic System Level (ESL) design is the key here, allowing designers to move to a new level of abstraction for both design and verification.

"Secondly, the challenges of manufacturing a well-yielding and reliable device as we move to 22nm will require a far more sophisticated physical implementation environment—one that accounts for physical effects in the design loop, and accounts for manufacturing variability in it's optimization routines.

"Finally, the manufacturing challenges also open significant opportunity for EDA in the manufacturing space. A great example of this is the September 17, 2008 announcement we did with IBM on a joint development program to enable manufacturing at the 22nm node."

Finally, given the roles already defined by Magma and Synopsys in solar, is there an opportunity for EDA in solar/PV?

According to Sawicki, as the photovoltaic devices have very simple and regular structures, most of the opportunity for EDA is not in logic design tools, but in material science, transistor-level device modeling, and manufacturing efficiencies with a focus on conversion efficiency and manufacturing cost reduction.

EDA's role in solar will be in the newer areas related to Design-for-Manufacturing and other manufacturing optimizations, he concludes.

Our last discussion on DFM will follow in a later blog post!

Top 10 global semicon predictions -- where are we today

It is always interesting to write semicon blogs! Lots of people come up to me with their own comments, insights, requests, etc. One such request came from a friend in Taiwan, who's involved with the semiconductor industry.

I was asked forthrightly what I thought of the top 10 global predictions, which I had blogged/written about some time back late last year.

Top 10 semicon predictions
For those who came in late, here are the 10 global predictions on semiconductors made at that time (late December 2007.

1. Semiconductor firms may have to face a recession year in an election year.
2. DRAM market looks weak in 2008.
3. NAND market will remain hot.
4. Power will remain a major issue.
5. EDA has to catch up.
6. Need to solve embedded (software crisis?) dilemma.
7. Consolidation in the fab space.
8. Capital equipment guys will continue to move to other market.
9. Spend on capital equipment to drop.
10. Mini fabs in developing countries.

Well, lot of water has flowed since those predictions were made. Let's see how things stand, as of now. The updated predictions would look something like these:

1. There have been signs of recession, but the industry has faced it well, so far. In fact, Future Horizons feels that if there is going to be a global economic recession, the chip industry (but not all companies) is in the best shape possible to weather the ensuing storm.

2. Memory market is changing slightly as well, though people are very cautious. According to Converge, memory market prices appear to be stabilizing. iSuppli has predicted a poor year for DRAM though!

3. NAND Flash could show some recovery later this year. Yes, Q1-08 QoQ sales seems to have slipped, but the market remains hopeful of a recovery. Even iSuppli warned of NAND Flash slowdown in 2008, while Apple slashed its NAND order forecast significantly for 2008! Keep those fingers crossed!!

4. Power remains a big issue, and will continue to be so. This will remain as we move up newer technology process nodes.

5. EDA is seemingly catching up with 45nm designs. Magma, Synopsys, and the other leading EDA vendors are said to be playing big roles in 45nm designs.

6. Fabless companies are gaining in strength. No doubt about it! The 2007 semicon rankings show that. Also, Qualcomm is now the leader in the top wireless semicon suppliers, displacing Texas Instruments.

7. There have been consilidations (or long term alliances) in: a) fab space b) DRAM space. In the fab space, Intel, Samsung and TSMC have combined to go with 450mm wafer fab line by 2012. And in the DRAM space, there have been new camps, such as Elpida-Qimonda, and Nanya-Micron partnering to take on Samsung. With the global semiconductor market seeing steady decline in growth rate, which would continue, look forward to more consolidations.

8. Investments in photovoltaics (PV) have eased the pressure on capital equipment makers and spend somewhat. In fact, 2007 will be remembered as the year when the PV industry emerged as a key opportunity for subsystems suppliers and provided a timely boost in sales for those companies actively addressing this market. Perhaps, here lies an opportunity for India.

9. Mini fabs -- these are yet to happen; so far talks only. In India, a single silicon wafer fab has yet to start functioning, even though it has been quite a while since the semicon policy was announced. Conversely, some feel that India should focus on design, rather than go after something as mature as having wafer fabs. However, several solar fabs -- from Moser Baer, Videocon, Reliance, etc., are quite likely.

10. Moving to 45nm from 32nm is posing more design challenges than thought. This is largely due to the use of new materials. Well, 45nm will herald a totally different structure -- metal gate/high-k/thin FET/deep trench design, etc. It will herald a new way of system design as well.

Now, I am not a semicon expert by any long distance, and welcome comments, suggestions, improvements from you all.

Semicon to grow 12pc in 2008: Future Horizons

If there is going to be a global economic recession, the chip industry (but not all companies) is in the best shape possible to weather the ensuing storm!

According to Malcom Penn, CEO, Future Horizons, we are dealing with a semiconductor industry in 'deep trauma.' He was delivering the company's forecast at the recently held International Electronics Forum (IEF) 2008 in Dubai, predicting a 12 percent growth this year despite signs of a wobbling US economy.

Is there a need to get back to the industry basics? “Semiconductors are a peculiar business; the only sane strategy is to bet the company regularly,” once remarked Dr Gordon Moore.

Penn noted that the current industry status is somewhat confused and uncertain. Short-term issues are dominating the agenda.

Longer-term structural trends are unclear. The traditional IDMs are currently going through a mid-life ‘new business model’ identity crisis, and the start-ups are struggling to even reach critical mass! And all of this has been happening amidst intense economic uncertainty

"Now is the time for strong nerves and determination," Penn said. According to him, the underlying industry fundamentals are sound and there is no end in sight to the 'make-lunch-or-be-lunch' ethos.

The emerging economies like India and China have so far been less affected by the financial market's turbulence. In fact, the emerging and developing economies were shifting the global growth dynamics.

Chip industry in best possible shape
A forecast health warning is: IF the global economy collapses, it will take the chip market with it. However, Future Horizons feels that if there is going to be a global economic recession, the chip industry (but not all companies) is in the best shape possible to weather the ensuing storm.

The ASPs are an enigma wrapped up in riddle. The course of ASPs (like love) never runs smooth. Wobbles happen! ASPs are also the perennial (and least understood) industry wild card. ASPs are generally driven by new IC designs, and that takes time (sometimes three to four years). Post-2001, value recovery lost one generation (130nm impact). The ASP recovery ‘wobbled’ in 2007 (memory and MPU price wars). Barring a recession, Future Horizons forecasts that ASPs will recover in 2008 (it has already started).

12 percent growth likely
Future Horizons' 2008 forecast summary and assumptions (as of May 2008) are -- ‘12 percent’ growth -- '10 percent' units / ‘2 percent’ ASP. There may be no global economic recession, although US/UK/Eurozone might wobble -- which they are! No significant inventory correction will probably take place, but there are always Q4>Q1 adjustments, and there's nothing special about that either.

There could be lower fab capacity expansion due to 2007/2008 capex slowdown, which is inevitable and irreversible. There is also a possibility of a more stable memory price erosion -- which means, back to the learning vs. bleeding curve, and prices have since hardened. If the global economy holds, the 2H-08 growth will likely be strong. This, if the capacity, ASP and units are all pulling together, which is said to be happening.

Therefore, Penn feels it is too early to call for a (major) downward revision. Q1 08 was a lot stronger than conventional wisdom feared.

"That’s the rational analysis, but semiconductors aren’t rational. It could just as easily be another single digit growth year," Penn added.

Danger signs to watch out for
So, what are the danger signs one should watch out for? These would be capacity -- it is hard to see how this can spoil 2008, provided unit growth holds up, but there is a need to watch capex. Another factor is demand -- the current IC unit demand is sustainable provided the economy holds up, so there is a need to watch the inventory.

Next comes the economy! The current outlook continues to be uncertain with risks all on the downside. ASPs are the key to recovery, but always the first line of defence. ASPs could still derail 2008, but the trends are encouraging.

What's driving the market?
In semiconductor 7.0 -- or the 7th decade of the transistor revolution, the same things, as always, are driving the market. These are: technology, legislation -- energy saving/conservation and structural -- the relentless analog to digital conversion. All of these are combining to do what the chip industry does best -- enabling something that was previously impossible. Penn contends, "This industry has nowhere near run out of steam!"

New applications continue to drive the market, with automotive, industrial and medical, mobile phones, and PCs and servers, dominating. The PC market is dominating, but going nowhere fast. Mobile phones have become more interesting, but have conflicting priorities. The challenges are: how to protect the existing cost structure and subscriber base and how to add useful and affordable value-add services! Evidently, "chipset suppliers love the high end, market loves the low end."

There is definitely an increasing automotive semiconductor content. A solid annual growth has been prediced (CAGR 2006-11) for vehicles -- 5.5 percent, systems -- 11.5 percent, and semiconductors -- 13.3 percent. Some other new areas are motor control and energy, as well as lighting and photovoltaic, besides medical electronics. Robotics is yet another interesting area.

Key industry issues
It is clear that more chips per wafer equals less cost per chip and more transistors per die equals more functionality. Several billion transistors gives phenomenal design flexibility as well. Considering total ICs and MOS ICs, in the MOS capacity build out by technology node, there has been no change in volume ramp profile despite the hype.

As for the evolution of the technology node, definitely, 45nm is a revolutionary step from 65nm. In all likelihood, 32nm will be a natural evolutionary. However, Penn cautioned that 22nm would be another ‘difficult’ transition!

There is no doubt that 65nm will be tomorrow’s leading-edge workhorse, having the same basic Si gate/SiO2/MOSFET structure. Nevertheless, 45nm will herald a totally different structure -- metal gate/high-k/thin FET/deep trench design, etc. Also, 45nm will herald a new way of system design.

Is fabless right?
Is Fablite a valid option? While there is nothing wrong with being fabless, people are just not sure whether the best starting point is being an IDM. Teamwork has to be perfectly orchestrated as competition is tough.

As for the market share dynamics, the top 10 companies (IDMs) have been losing share. Fabless share has been growing, but it is still relatively small.

Coming to the realities of the foundry market, TSMC's lead is now unassailable. Were it an IDM, it would be No. 2, challenging Intel and passing Samsung. Moving more into design looks inevitable.

Finally, execution, and not technology, is everything! Execution has and will continue to make the difference. Applications (software) will play the role of the key differentiator as well, and it has value. Design is the means to an end, and not the end.

From the chip industry's perspective, the electronics market was traditionally Japan, North America and Western Europe. It now encompasses the entire Asian rim, China, Eastern Europe and India. Far from maturing, the chip industry itself is still in its volatile, high-growth phase, with at least a further 20 years of strong growth in prospect. Penn said, "The underlying growth drivers for chips has never been better."

Back to basics
We started with the need to get back to industry basics. We end in the same way! Stick to basics like:

* Don’t invest in low cost areas just because they are cheap -- they have a habit of becoming high cost tomorrow, plus the hidden extras.
* Don’t make outsourcing decisions just because they are easy -- especially if there’s no way back.
* Don’t make strategic cut-backs just to trim the bottom line -- some decisions, e.g., R&D, take a long time to impact, then it’s too late.
* Stop looking for high volume/high value market niches -- they don’t exist, need to learn how to compete
* Do show strong leadership
* Do have a long-term plan and stick with it -- even if it negatively impacts ‘the next quarter’ balance sheet
* Do show a commitment and determination to succeed
* Do stay focused and resistant to external meddling
* Do execute ruthlessly -- this is the key competitive differentiator)
* Do … just do it with passion -- it’s the passion that makes the difference

Semicon outlook 2008: Global market likely to grow 6-11 percent amid recession fears

While a majority of analysts at a recent panel discussion on global semiconductor outlook predicted semiconductor growth in the range of 6-11 percent during 2008, some other panelists predicted 2008 to be flat year or a year of negative growth.

There were fears of a possible recession in 2008, along with concerns surrounding consumer spend that could be hit by higher oil prices and the US mortgage crisis.

This panel discussion was organized last week by Semiconductor International, USA. Here is the full report.

Semi forecasts mixed for 2008

Amid concerns of a possible recession in the US economy in 2008, analysts at a recent Webcast hosted by Semiconductor International, were divided in their forecasts for the coming year. A majority predicted semiconductor growth to be in the range of 6-11 percent during 2008, while some others predicted 2008 to be flat year or a year of negative growth.

Anne Craib, director of Market Research, International Affairs and Finance, Semiconductor Industry Association (SIA), said the global economic situation needed to be factored in, as well as its impact on consumer demand.

She said: "Semiconductor demand is driven over 50 percent by consumer demand currently. That is something we should increasingly be aware of. Areas like gas prices and the home mortgage market are things that we previously would not have paid much attention to that we have had to take into account in our forecasting this cycle.” She was confident of the semiconductor industry reaching 7-8 percent CAGR during 2008.

Steve Szirom, President, InsideChips.com, added that many economists were predicting recession in 2008. He said: "The demand-supply balance should be somehwat better than this year. We may have a demand driven recession." He adopted a pessimistic view for 2008, predicting -8 percent growth.

DRAM weak, NAND bright

Gary Grandbois, principal analyst for iSuppli Corp., noted: “We have reduced our forecast to 7.5 percent for 2008 and think it might go lower than that. We think it’s going to be a negative first half. Certainly in the DRAM area, it’s looking very poor. We think it will improve in the second half, almost mirroring 2007, but giving us a far weaker year in 2008 than we’ve expected.”

Richard Gordon, Managing Vice President, Semiconductors, Gartner Dataquest Research, agreed with Grandbois, adding that DRAM would see a negative side in 2008. "Our forecast is 6 percent for 2008, and it doesn't factor in the US recession," he said.

While the DRAM market has been predicted to be negative next year, analysts see a positive market for NAND in 2008. New applications, such as WUSB (wireless USB), increase in cell phones, higher content in portable media players, etc., are likely to drive growth.

Commenting further on the outlook for 2008, Moshe Handelsman, President, Advanced Forecasting Inc., noted that 2007 would be the peak of current IC cycle. "From that point on, the underlying demand for semiconductors will decline and decline in 2008. We are negative about 2008," he added.

Carl Johnson, Executive Director, Research Infrastructure, concurred that the industry had become much more global. "We now have to look at the mortgage debacle, etc. Consumers will be very tight in first half of this year." He added, "I would say, next year's going to be flat."

Mike Cowan, an independent semiconductor industry analyst, said the growth would be about 8.15 percent during 2008. "The dynamics of the market and the industry will change month-to-month as well," he quipped.

Capex likely to dip in 2008

Regarding capex in 2008, Carl Johnson of Research Infrastructure, expects the next year to be bumpy as far as capital spending is concerned. "We're in a downturn right now. Foundries, who are investing lot more money in older process generations, and that is a function of some of the other older IDMs and fabs, are actually shutting down and saying, 'we can go over to the foundries and process wafers for less than what we can do it on our own'. We are seeing lot of consolidation within the fab space. Mid-level players are consolidating. The customer base is clearly narrowing."

The cost of designing some of these leading-edge devices, and getting them to market, and then following it up with another product, if you don't want to be a one-product guy, is a real challenge. That is limiting the number of players that are going into the mega fabs. So, the field is narrowing in 65nm, and 45nm, and as we get to below 45nm, the field is going to get much, much narrower.

According to him, capital spending is likely to be down in 2008. "I am predicting 10 percent down next year. There's also going to be a great consolidation in the devices manufacturing community, and also in the capital equipment community. We are seeing a number of M&A activities in the capital equipment business. It will also go into the supply chain business."

Gartner's Richard Gordon said the research firm was forecasting capex to be down by -15 percent in capex in 2008, and that includes -30 percent in the DRAM sector. He added: "Looking at the individual companies in the DRAM space, I won't be surprised to see that go even lower. So, -15 percent in capex can get even worse as 2008 unfolds. We will see it coming back. But, it will take a while for demand to catch up with supply."

EDA industry in catch-up mode

The EDA industry is said to be lagging behind the semiconductor industry at the moment, and is in the catch-up mode, according to Gary Smith, President, Gary Smith EDA.

Commenting on the outlook for the EDA market, Smith said the EDA industry is in a lttile unusual position. He said: "The market's been flat for the past four years. Tools for 65nm, 45nm silicon design have also been delayed." The R&D was not put in because of the recession. "Right now, we are in a position of lag in the market," he added.

EDA tools cover two process generations. The industry is just starting to introduce 65nm and 45nm tools. That generation is being called the DFM generation tool. Smith said: "It is even more important to the semiconductor industry as we run into manufacturing problems that they are relying on design tools to solve, rather than on semiconductor equipment." That's a major shift in the market!

EDA to grow 7.8 percent in 2008

According to him, the industry is now now into a pretty good growth area. "We were 11 percent last year, 10.2 percent to come in this year. We will be a bit down next year at 7.8 percent," he forecast. This has been attributed mainly to the EDA industry's lag in the market. "Some are moving to 32nm. And certainly, a lot of work is being done in 45nm," he added.

Smith noted: "The EDA industry is in the catch-up mode. We will lag them. We are expecting the downturn to really hit us in 2009. However, we are not an industry that goes negative often. No matter what you guys do, you still have to design something. So, when you go into recession, typically, the way you get out of recession is you generally design your way out!"

DFM, ESL growth drivers

Among the growth drivers is the DFM (design for manufacturing) issue, which is increasingly getting more complex. There is said to be a move to restrict the design rules that is in place now for 45nm. "We are going to see major changes in 32nm; that'll have impact on tools," he added.

The other issue is parallel computing that has become a major task for the EDA industry. "With signal threading, we can no longer handle designs over 100 million gates. Of course, at 45nm, you can do a 100mn gates. That rewriting process is another issue that is also slowing out down. That's a full three-year re-write," Smith said.

Further, EDA is also starting to move up into the ESL. The electronic-system level (ESL) is going to shift the EDA market more into the systems market, and serve less on its dependency on the semiconductor world.

New fabs in India, China

There have been a lot of announcements made regarding new fabs, especially in places such as India, China and Brazil.

Gary Grandbois at iSuppli said: "Brazil is a better example. India just announced that they are building new fabs. What we saw at the turn of the century is that the industry split into two areas -- one traditional components manufacturer and second is the SoC manufacturer. Those are the companies that need leading edge fabs."

According to him, the cost of R&D was going out of sight for process development. "We're also seeing consolidation of research groups. We expect that come down to five consortiums or less. All companies can afford do their own process development once the basic process has been developed."

There are going to be different types of fabs. With globalization, lot of countries may decide they want to have a fab. Brazil announced one. "You're going to see them all over the world. The market's going to change," he added.

Anne Craib from the Semiconductor Industry Association said: "If you look at the cost structure, it costs over $1bn to build and operate a fab in the US. The question is where is the fab going to be located? The US companies will continue to be major players. Again, the question is: where is it going to be economically feasible? The interest is outside of the US."

New elements likely in 32nm

On the subject of integration of MEMS, 3D, etc., Carl Johnson from Research Infrastructure said, "A very large topic with the design community is big change in computer architecture -- the big change is the multicore -- that's the biggest driver now."

Jim Feldhan, President, Semico Research Corp., noted that the industry is going to hit limits with silicon processing at some point of time. "We have to bring in new elements. In 32nm, there'll be only a handful of companies who can push real hard there and can afford it."

Push to 450mm fabs unlikely?

Finally, is there be going to be a push to 450mm fabs and how's the impact going to be like?

iSuppli's Gary Grandbois, said that curently the industry was expecting that it would need to abandon silicon in 2020. "If we don't have any silver bullets by then, we are going to use nano stuff to augment CMOS. We don't know what that's going to be."

He added: The issue is: are we going to use silicon at all in 2020? If we start developing equipment for 450mm, we're not going to have that very soon. What they have to consider, what is the payback for that move?"

We would love to hear from you on how you see the semiconductor industry going in 2008.

Growth drivers for semiconductor industry

Michael J. Fister, president and CEO, Cadence Design Systems Inc., who was in India for the CDNLive event, delivered a wonderful keynote at the recently held CDNLive. Here's what he had to say!

The semiconductor industry is maturing. Since 2000, the industry’s annual growth rate has experienced extreme highs and lows.

Though the semiconductor industry's revenue growth will be low in 2007, the good news is that growth rates are smoothing out as costly fabs demand consistent production. Wireless communications, computers, and consumer products continue to be the growth drivers for semiconductors. A couple of the semiconductor technology trends driving electronic design and product development are:

* More designs at advanced nodes — Beginning this year, 90nm designs will outnumber those at 130nm. Meanwhile, 65nm is design activity is ramping up and advanced designs are targeting 45nm.

* Growth in transistor count and logic — Not only are transistor counts increasing according to Moore’s Law, those transistors are being used to create more functions -– and therefore more complexity -– on a single chip, not just adding memory to the existing designs.

A related trend is that the amount of chip production outsourced to foundries continues to grow, with many Integrated Device Manufacturers (IDMs) moving to a 'Fab-lite' strategy for advanced nodes. This is happening as design is becoming a greater product differentiation than production.

Note that Fister's reference to Fab-lite is interesting, even though lot of new investments are said to be getting into, and he himself says, "costly fabs demand consistent production." There is another point that should not be overlooked -- the one concerning Qualcomm, a fabless company, making it to the Top 10 semicon companies, for the first time.

Coming back the Cadence CEO, all of these trends create two kinds of challenges for chip design. These are: 1) manufacturability at advanced process nodes like 90nm and below, and 2) increased complexity and scale of chip design of system-on-chip (SoC).

Design solutions today must address these challenges, and increase team productivity and schedule predictability. To accomplish this, Cadence is focused on a holistic approach to the design flow. The Cadence Low-Power Solution and the Encounter Timing System are good examples of this holistic approach addressing the challenges of escalating scale and complexity.

The same holistic approach is shown in Cadence’s approach to manufacturability, which is to integrate design for manufacturability (DFM) into all aspects of the design flow, rather than just apply DFM techniques as a post-design step.

Challenges for IC industry and Dr. Gargini's lessons

Those who were fortunate enough to attend the recently held SEMICON WEST in San Francisco had the pleasure of attending a great session on the past. present and future challenges for the IC industry by Dr. Paolo Gargini, Director of Technology Strategy at Intel.

For those who may not have the time to read this article, here's a snippet of what Dr. Gargini had to offer. The first lesson, he said, was that, "Something right may still happen even when everything seems to be going wrong.” However, challenges that were continuously posed also needed to be addressed at the earliest, in order to keep moving forward.

Many also predicted several times that some limit would be reached – that chip development would never get below ten nanometers, or below five nanometers. However, the industry was able to produce components with a gate oxide at about 1.2 nanometers.

Later, the game changed to scaling, which led to Gargini’s second lesson – “Predictors of engineering limits have always been proven wrong by the right improvements.” Shrinking silicon technology of the 1990s kept the industry moving forward.

His third lesson was, “It would be wrong to believe that the right fundamental limits don’t exist.” The fourth lesson was, “It is wise to look for the right solutions before things start going wrong.” Dr. Gargini recalled how Intel had announced that 45nm generation was ready. That it included high-k metal gates was only disclosed this January giving Intel the time to work on yields, enhancements, reliability problems, etc.

Gargini quoted Gordon Moore as saying that introduction of high-k metal gates was the single most important innovation in semiconductor manufacturing of the last 40 years!

Interestingly, a few weeks ago, the PULLNANO Consortium announced breakthrough results for 32nm/22nm. Among other things, the PULLNANO consortium has fabricated a functional SRAM using innovative MOS transistors whose device architecture differs significantly from that of transistors used in 45nm technology node.

These transistors are built using a low power consumption approach based on Fully Depleted Silicon On Insulator (FDSOI), coupled with a gate stack composed of a high-K gate dielectric and a single metal electrode stack. This is said to be the first time that such a compact SRAM cell has been fabricated using FDSOI, high-k dielectric and metal gate together.

Coming back to Dr. Gargini, his fifth lesson was, "It would be wrong to delay taking action and not do the right thing at the right time." According to him, there was a need for re-examining the opportunities for reviewing “old” theories and techniques that didn’t work on silicon.

Paradigm shift indeed in semicon

Going through an article written by Dr. Wolfgang Ziebart, Member of the Management Board, President and CEO, Infineon Technologies, in Financial Times Deutschland, one cannot help but appreciate the great paradigm shift that has indeed taken place in the semiconductor industry.

The article titled: A paradigm shift in the semiconductor industry: Could this be the end of Moore’s Law? focuses on how changing technologies are indeed making life difficult for most market players to keep pace with all those changes.

The technical possibilities for shrinking chips have far from reached their limits at 65nm. There are preparations already on for 45nm and development work for 32nm has already started!

When PULLNANO announced breakthrough results for 32/22nm, did it surprise many? The PULLNANO consortium has fabricated a functional SRAM using innovative MOS transistors whose device architecture differs significantly from that of transistors used in 45nm technology node.

It talks about a compact SRAM cell that has been fabricated using FDSOI (Fully Depleted Silicon On Insulator), high-k dielectric and metal gate all together.

PULLNANO has demonstrated that the material and integration schemes used in 45nm generation can be modified to provide a robust solution at 32nm. It has also proposed an innovative new architecture that could provide even higher performance at 32nm and 22nm, using the so-called 'air gap' technique.

I do remember Dr Pradip Dutta of Synopsys India telling me about two months ago about 32nm, during a course of a telephonic conversation about ndia's moves in the semicon space.

After that conversation, I was wondering how quickly semicon technology had started to move. How quickly, from a has-been all these years, India was suddenly emerging as a semicon base to reckon with. How quickly, the geometry had moved from 90nm to, now, 22nm!

Dr Dutta also added that there would be more emphasis in India on doing high-end designs. In fact, whether it is frequency, number of gates, high complexity, etc., all of those would be driven by applications. India is now ready for doing high-end complex designs.

Indian companies are now definitely excelling in the design services sector. Some of them have also grown significantly. It is believed that they have also taken a load off the international design services company. Some of these Indian companies are now also developing their own IPs -- a paradigm shift in itself!