SANTA CLARA, USA: GSI Technology Inc., a leading provider of high-performance SRAM products incorporated primarily in networking and telecommunications equipment, has signed and closed definitive agreements with Sony Electronics Inc. under which GSI acquired substantially all of the assets related to Sony’s SRAM product line.
At closing, GSI paid Sony approximately $5.2 million in cash. GSI will make a further cash payment to Sony of approximately $1.7 million following a post-closing adjustment to reflect actual product inventory on hand at closing.
GSI will also make future cash payments based on the sale of certain acquired SRAM products over an eight quarter period. The acquisition will be accounted for under the purchase method of accounting.
The acquisition will not have a significant impact on GSI’s total revenues or, except for adjustments required by purchase accounting rules, on its operating results for the second fiscal quarter ending September 30, 2009.
Based on historical sales data and current sales projections, GSI believes that the new product line will generate additional revenues of approximately $1 million in the third quarter ending December 31, 2009 and expects that the new product line should generate quarterly revenues of approximately $2 million by the quarter ending September 30, 2010.
GSI also expects that, after a transition period of one to two quarters, gross profit margins comparable to GSI’s overall gross margins will be achieved.
“The acquisition of Sony’s portfolio of advanced SRAM products is an excellent strategic fit for GSI and strengthens our position as a leading supplier of high performance SRAM products,” said Lee-Lean Shu, Chairman and CEO.
“The acquisition further extends our broad SRAM product portfolio and provides us with additional scale to support our ongoing investment in research and development.”
Showing posts with label SRAM. Show all posts
Showing posts with label SRAM. Show all posts
Monday, August 31, 2009
Wednesday, April 22, 2009
IMEC successfully transfers MemoryVAM to Samsung
BELGIUM: IMEC has successfully transferred MemoryVAM (Memory Variability Aware Modeling), the first EDA tool for statistical memory analysis, to Samsung Electronics. The tool predicts yield loss of SRAMs caused by the process variations of deep-submicron IC technologies.
IMEC's MemoryVAM is an essential tool to avoid already at design time the most likely reasons for failure, anticipating and correcting weak design spots before tape-out, and hence avoiding redesign spins after processing. The tool also provides key help to memory and system designers to estimate yield loss due to changes of for example cycle time, access time and power consumption (static/dynamic) caused by process variations.
"With MemoryVAM IMEC completes a missing steppingstone in industrial and academic state-of-the-art Design-For-Manufacturing flows which lacked such modeling capabilities for memories;" said Rudy Lauwereins, Vice President Smart Systems Technology Office at IMEC. "This is especially interesting for embedded SRAMs, which are considered to be the most sensitive component to process variations of today's systems-on-chip. We are excited that the tool is now being successfully used by the product engineering design teams at Samsung Electronics."
"With collaboration with IMEC, a new novel statistical analysis tool MemoryVAM has become available in our embedded SRAM design." said Kyu-Myung Choi, Vice President of Design Technology Team at Samsung Electronics. "We expect that MemoryVAM will be helpful for parametric yield modeling of embedded SRAM design and for understanding the unknown gap between design and silicon results due to process variability in deep sub-micron technology below 45nm."
MemoryVAM is part of IMEC's Variability Aware Modeling (VAM) flow which is the first holistic flow capable of percolating process variations all the way from the process technology up to the System on a Chip (SoC) level. VAM enables to track the reasons for yield loss and the relative likelihood of such failure. Unlike most of the statistical analysis techniques, VAM is unique in its kind by accurately keeping track of all statistical process, design and environmental correlations tightly linked together and across abstraction levels.
MemoryVAM builds on IMEC's revolutionary method to analyze performance metrics of semiconductor memories under process variations. The method requires mainly three input items. The first is a transistor level netlist description of a segment of the memory describing all circuitry involved from input to output. The second one is a set of parameters describing the internal architecture of the memory, thus how the memory is built from the segment information, including redundancy and error correction code infrastructure.
The third one is information about the variability of the devices and interconnects used in the underlying technology. This information can be provided in either the form of statistical distributions of certain transistor parameters, scattered data obtained via statistical simulation of the device or just plain data set obtained via silicon measurements.
The power of MemoryVAM lies in the analysis of parameters of the memory that can be directly embedded in the input netlist by the designer. These are then used to carry out the implementation of the method, without requiring additional custom modeling steps from the user.
The key to this strategy is the ability to complement the analysis of a nominal memory model under test with statistically sampled variants of the devices. This is done by using an in-house developed statistically enhanced Monte Carlo technique, although it also allows the usage of any other available enhanced sampling technique. With this novel and fast analytical technique, statistical information on the critical path percolates to the complete SRAM organization level, resulting in a realistic prediction of the yield as perceived by the memory tester and/or equivalent BIST (built-in-self-testing) technique.
IMEC's MemoryVAM is an essential tool to avoid already at design time the most likely reasons for failure, anticipating and correcting weak design spots before tape-out, and hence avoiding redesign spins after processing. The tool also provides key help to memory and system designers to estimate yield loss due to changes of for example cycle time, access time and power consumption (static/dynamic) caused by process variations.
"With MemoryVAM IMEC completes a missing steppingstone in industrial and academic state-of-the-art Design-For-Manufacturing flows which lacked such modeling capabilities for memories;" said Rudy Lauwereins, Vice President Smart Systems Technology Office at IMEC. "This is especially interesting for embedded SRAMs, which are considered to be the most sensitive component to process variations of today's systems-on-chip. We are excited that the tool is now being successfully used by the product engineering design teams at Samsung Electronics."
"With collaboration with IMEC, a new novel statistical analysis tool MemoryVAM has become available in our embedded SRAM design." said Kyu-Myung Choi, Vice President of Design Technology Team at Samsung Electronics. "We expect that MemoryVAM will be helpful for parametric yield modeling of embedded SRAM design and for understanding the unknown gap between design and silicon results due to process variability in deep sub-micron technology below 45nm."
MemoryVAM is part of IMEC's Variability Aware Modeling (VAM) flow which is the first holistic flow capable of percolating process variations all the way from the process technology up to the System on a Chip (SoC) level. VAM enables to track the reasons for yield loss and the relative likelihood of such failure. Unlike most of the statistical analysis techniques, VAM is unique in its kind by accurately keeping track of all statistical process, design and environmental correlations tightly linked together and across abstraction levels.
MemoryVAM builds on IMEC's revolutionary method to analyze performance metrics of semiconductor memories under process variations. The method requires mainly three input items. The first is a transistor level netlist description of a segment of the memory describing all circuitry involved from input to output. The second one is a set of parameters describing the internal architecture of the memory, thus how the memory is built from the segment information, including redundancy and error correction code infrastructure.
The third one is information about the variability of the devices and interconnects used in the underlying technology. This information can be provided in either the form of statistical distributions of certain transistor parameters, scattered data obtained via statistical simulation of the device or just plain data set obtained via silicon measurements.
The power of MemoryVAM lies in the analysis of parameters of the memory that can be directly embedded in the input netlist by the designer. These are then used to carry out the implementation of the method, without requiring additional custom modeling steps from the user.
The key to this strategy is the ability to complement the analysis of a nominal memory model under test with statistically sampled variants of the devices. This is done by using an in-house developed statistically enhanced Monte Carlo technique, although it also allows the usage of any other available enhanced sampling technique. With this novel and fast analytical technique, statistical information on the critical path percolates to the complete SRAM organization level, resulting in a realistic prediction of the yield as perceived by the memory tester and/or equivalent BIST (built-in-self-testing) technique.
Monday, December 8, 2008
Memory market to witness another negative sales growth in 2009
This is a continuation from my previous blog on the outlook for the global semiconductor industry, and iSuppli's ranking of the Top 20 global semiconductor companies.
Thanks to Jon Cassell at iSuppli, I also got into a conversation with Nam Hyung Kim, Director & Chief Analyst, iSuppli. Kim touched upon the outlook for DRAM and the memory market as a whole.
Further analyzing iSuppli's top 20 rankings, among the leading memory makers, Hynix has performed the worst. On this aspect, Kim says that DRAM sales is likely to decline by 20 percent in 2008. Thus, Hynix’s performance is not far from overall challenging status considering it also scaled NAND flash business back dramatically.
On another note, Qimonda is also among the strugglers, and there have been whispers about its possible bankruptcy. However, iSuppli did not comment on this topic.
So, how much longer will it take before the memory market can come out of its current woes? Kim adds: "The memory industry inevitably will experience another negative sales growth in 2009. However, the rate of sales decline will be much lower than that of 2008.
"The year 2009 will be the third year of the memory market downturn. Therefore, supply growth reduction will take place fast, resulting in lower price drop compared to 2008."
Finally, what's the way forward for DRAM, NOR and SRAM? Kim asserts that iSuppli expect the following sales growth in 2009 (preliminary):
* DRAM: single digit percentage sales decline; and
* NAND, NOR, SRAM will experience mid to high teens sales decline.
Thanks to Jon Cassell at iSuppli, I also got into a conversation with Nam Hyung Kim, Director & Chief Analyst, iSuppli. Kim touched upon the outlook for DRAM and the memory market as a whole. Further analyzing iSuppli's top 20 rankings, among the leading memory makers, Hynix has performed the worst. On this aspect, Kim says that DRAM sales is likely to decline by 20 percent in 2008. Thus, Hynix’s performance is not far from overall challenging status considering it also scaled NAND flash business back dramatically.
On another note, Qimonda is also among the strugglers, and there have been whispers about its possible bankruptcy. However, iSuppli did not comment on this topic.
So, how much longer will it take before the memory market can come out of its current woes? Kim adds: "The memory industry inevitably will experience another negative sales growth in 2009. However, the rate of sales decline will be much lower than that of 2008.
"The year 2009 will be the third year of the memory market downturn. Therefore, supply growth reduction will take place fast, resulting in lower price drop compared to 2008."
Finally, what's the way forward for DRAM, NOR and SRAM? Kim asserts that iSuppli expect the following sales growth in 2009 (preliminary):
* DRAM: single digit percentage sales decline; and
* NAND, NOR, SRAM will experience mid to high teens sales decline.
Wednesday, July 11, 2007
Paradigm shift indeed in semicon
Going through an article written by Dr. Wolfgang Ziebart, Member of the Management Board, President and CEO, Infineon Technologies, in Financial Times Deutschland, one cannot help but appreciate the great paradigm shift that has indeed taken place in the semiconductor industry.
The article titled: A paradigm shift in the semiconductor industry: Could this be the end of Moore’s Law? focuses on how changing technologies are indeed making life difficult for most market players to keep pace with all those changes.
The technical possibilities for shrinking chips have far from reached their limits at 65nm. There are preparations already on for 45nm and development work for 32nm has already started!
When PULLNANO announced breakthrough results for 32/22nm, did it surprise many? The PULLNANO consortium has fabricated a functional SRAM using innovative MOS transistors whose device architecture differs significantly from that of transistors used in 45nm technology node.
It talks about a compact SRAM cell that has been fabricated using FDSOI (Fully Depleted Silicon On Insulator), high-k dielectric and metal gate all together.
PULLNANO has demonstrated that the material and integration schemes used in 45nm generation can be modified to provide a robust solution at 32nm. It has also proposed an innovative new architecture that could provide even higher performance at 32nm and 22nm, using the so-called 'air gap' technique.
I do remember Dr Pradip Dutta of Synopsys India telling me about two months ago about 32nm, during a course of a telephonic conversation about ndia's moves in the semicon space.
After that conversation, I was wondering how quickly semicon technology had started to move. How quickly, from a has-been all these years, India was suddenly emerging as a semicon base to reckon with. How quickly, the geometry had moved from 90nm to, now, 22nm!
Dr Dutta also added that there would be more emphasis in India on doing high-end designs. In fact, whether it is frequency, number of gates, high complexity, etc., all of those would be driven by applications. India is now ready for doing high-end complex designs.
Indian companies are now definitely excelling in the design services sector. Some of them have also grown significantly. It is believed that they have also taken a load off the international design services company. Some of these Indian companies are now also developing their own IPs -- a paradigm shift in itself!
The article titled: A paradigm shift in the semiconductor industry: Could this be the end of Moore’s Law? focuses on how changing technologies are indeed making life difficult for most market players to keep pace with all those changes.
The technical possibilities for shrinking chips have far from reached their limits at 65nm. There are preparations already on for 45nm and development work for 32nm has already started!
When PULLNANO announced breakthrough results for 32/22nm, did it surprise many? The PULLNANO consortium has fabricated a functional SRAM using innovative MOS transistors whose device architecture differs significantly from that of transistors used in 45nm technology node.
It talks about a compact SRAM cell that has been fabricated using FDSOI (Fully Depleted Silicon On Insulator), high-k dielectric and metal gate all together.
PULLNANO has demonstrated that the material and integration schemes used in 45nm generation can be modified to provide a robust solution at 32nm. It has also proposed an innovative new architecture that could provide even higher performance at 32nm and 22nm, using the so-called 'air gap' technique.
I do remember Dr Pradip Dutta of Synopsys India telling me about two months ago about 32nm, during a course of a telephonic conversation about ndia's moves in the semicon space.
After that conversation, I was wondering how quickly semicon technology had started to move. How quickly, from a has-been all these years, India was suddenly emerging as a semicon base to reckon with. How quickly, the geometry had moved from 90nm to, now, 22nm!
Dr Dutta also added that there would be more emphasis in India on doing high-end designs. In fact, whether it is frequency, number of gates, high complexity, etc., all of those would be driven by applications. India is now ready for doing high-end complex designs.
Indian companies are now definitely excelling in the design services sector. Some of them have also grown significantly. It is believed that they have also taken a load off the international design services company. Some of these Indian companies are now also developing their own IPs -- a paradigm shift in itself!
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