Mentor Graphics: DFM is where all the value is!

As promised, here is the concluding part of my discussion with Joseph Sawicki, vice president & GM, Design to Silicon Division, Mentor Graphics.

We went over the design for manufacturing (DFM) challenges and how yield can be improved. He also touched upon the design challenges in 45nm and 32nm, respectively.

Given that the semiconductor industry does speak a lot about DFM, what steps are being taken to improve on the overall yield?

According to Sawicki, in the VLSI microchip era, yields started at 60-70 percent, and so DFM wasn't required. However, in the nanochip era, DFM is where all the value is. [VLSI Research.]

Joseph Sawicki, vice president & GM, Design to Silicon Division, Mentor GraphicsHe added that at smaller geometries, manufacturing variability has a much greater impact on timing, power dissipation, and signal integrity. Traditional guardbanding is no longer sufficient to guarantee competitive performance at acceptable yields, and excessive design margins erase the advantages sought by going to the next node in the first place.

Moving to advanced technologies without dealing effectively with manufacturing variability can actually put a design at a competitive disadvantage due to low parametric yield.

"Successful IC implementation requires a detailed understanding of how variability affects both functional and parametric yield. Customers need a manufacturing-aware engineering approach that extends across the entire physical implementation life cycle, starting with cell library development and extending through place and route, physical verification, layout optimization, mask preparation, testing, and failure analysis.

"They need a design flow that helps them "co-optimize" for both performance and yield simultaneously, based on accurate models of manufacturing process variability. The ability to do this quickly and effectively can give IC designers a powerful competitive advantage," Sawicki said.

There is no silver bullet! It takes a broad-based, well-integrated approach to have a significant and consistent impact on manufacturability.

According to him, Mentor Graphics provides a complete manufacturing-aware design-to-silicon solution addressing random particle effects, small-scale device and interconnect interactions, lithographic distortions and process window variations, and thickness variations resulting from chemical-mechanical polishing (CMP) and variable film deposition and etch rates.

"Our tools incorporate comprehensive, highly-accurate models that have been tuned and verified for specific manufacturing environments, and address every stage of the digital IC implementation life cycle," he added.

So, how is Mentor handling 45nm and 32nm design challenges?

Sawicki added: "Advanced process nodes present challenges at every stage of IC implementation, from place-and-route, through physical verification, layout enhancement, testing and yield analysis. Mentor has a complete design-to-silicon flow that addresses the critical challenges of IC implementation at every stage."